How to select parameters for Equivalent Time Sampling

[Altera_Forum]

I have a Nios system with Qsys components such as Interval timer, UART, SDRAM and some PIOs. My system specifications are DE0 Nano, Quartus 12.1 sp1, Altera monitor program. Nios II system are interfacing with several VHDL blocks. 

I am able to read data from FPGA to Nios processor, then transmit this data to Uart component created in Qsys using direct register method (IORD_ALTERA_AVALON_UART_STATUS (UART_BASE); IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE, txdata);etc). I am using USB-to-Serial interface to the board FTDI UM245R module. I am able to read serial port and plot the graph real time in Matlab. However, I am having the issue where there is aliasing when I tried to reconstruct a sinusoidal waveform. This is because the incoming signal is 50Hz and the serial port receive rate is just 8 Hz. I added a timer in my C code and I am able to get a perfect sinusoidal waveform with no aliasing, but I can't explain why. I googled and I know that what I was doing is actually "Equivalent Time Sampling" (ETS) concept which is very common in sampling oscilloscope where incoming signal has a higher sampling frequency than oscilloscope's sampling rate and can only be used on repetitive signal such as sinusoidal waveform. Basically, the ETS requires a first trigger, take first sample, wait for for rearm time, second trigger, delay, take second sample... but i failed to find a way to calculate those rearm time and delay...  int counter = 0x305600; IOWR_ALTERA_AVALON_TIMER_PERIODL( TIMER0_BASE, (counter & 0xFFFF) );//lower significant bits for start value IOWR_ALTERA_AVALON_TIMER_PERIODH( TIMER0_BASE, ((counter>>16) & 0xFFFF) ); //higher significant bits for start value IOWR_ALTERA_AVALON_TIMER_STATUS( TIMER0_BASE, 0 ); //clear timeout IOWR_ALTERA_AVALON_TIMER_CONTROL( TIMER0_BASE, 0x4 );//start timer while((IORD_ALTERA_AVALON_TIMER_STATUS( TIMER0_BASE ) & ALTERA_AVALON_TIMER_STATUS_TO_MSK) == 0 ) { }   Thank you in advance

[Altera_Forum]

ETS is a neat concept but it is used for signal frequencies in the MHz. If your sinewave is 50Hz, then you have no reason to be using ETS. 

 1) What is the FPGA's sample frequency. If your base clock is 50MHz, then even by sampling with NIOS you should get at least 10kHz (just approximating) of ADC sampling rate. Use a timer to trigger ADC reads (in the timer ISR) 2) Buffer the samples in a FIFO, on chip ram, or sdram 3) Transmit data from FIFO to PC using USB (what is your baud rate - 9600, 115200 ??). 4) Reconstruct in Matlab - you know the sampling rate of your data (see 1), you can reconstruct your signal - there will be a delay but that shouldn't be a problem, unless you want exactly real time....

[Altera_Forum]

--- Quote Start ---  ETS is a neat concept but it is used for signal frequencies in the MHz. If your sinewave is 50Hz, then you have no reason to be using ETS.  1) What is the FPGA's sample frequency. If your base clock is 50MHz, then even by sampling with NIOS you should get at least 10kHz (just approximating) of ADC sampling rate. Use a timer to trigger ADC reads (in the timer ISR) 2) Buffer the samples in a FIFO, on chip ram, or sdram 3) Transmit data from FIFO to PC using USB (what is your baud rate - 9600, 115200 ??). 4) Reconstruct in Matlab - you know the sampling rate of your data (see 1), you can reconstruct your signal - there will be a delay but that shouldn't be a problem, unless you want exactly real time....  --- Quote End ---     Thanks for your reply...The reason I am asking this question is that, I think I am doing the ETS in some sense, resulting in correct output being plotted in Matlab. But I have no idea whether ETS is implemented in Nios ii or in Matlab?  I am sending data from fpga (nios ii processor) to serial port and Matlab access the serial port and plot real time graph. The Nios II is 50MHz, so it has no issue to receive the data from fpga which is 50Hz  If the serial port receive rate is just 8Hz, but the data sent to serial port is 50Hz, what approach is Nios II using to digitize the samples? Does it have anything to do with equivalent time sampling (ETS)? I could not find any links between Nios II and ETS, correct me if I am wrong.  Appreciate any inputs.. thank you

[Altera_Forum]

--- Quote Start ---  ETS is a neat concept but it is used for signal frequencies in the MHz. If your sinewave is 50Hz, then you have no reason to be using ETS.  1) What is the FPGA's sample frequency. If your base clock is 50MHz, then even by sampling with NIOS you should get at least 10kHz (just approximating) of ADC sampling rate. Use a timer to trigger ADC reads (in the timer ISR) 2) Buffer the samples in a FIFO, on chip ram, or sdram 3) Transmit data from FIFO to PC using USB (what is your baud rate - 9600, 115200 ??). 4) Reconstruct in Matlab - you know the sampling rate of your data (see 1), you can reconstruct your signal - there will be a delay but that shouldn't be a problem, unless you want exactly real time....  --- Quote End ---    Hi Krasner, sorry for poor understanding, I just read carefully about ETS and you are absolutely right about ETS being not a good option here... So, I wanted to go for the buffering approach you are stating here, I found a few references, I checked at the Qsys, there are a few built-in fifo  1.Can we combine both uart ip core with fifo core, or do you mean they are to be done separately?  2. I am confused whether I should use an avalon fifoed uart or any fifo will do? I know there is on-chip fifo memory in Qsys, i am using SDRAM in my system  3. May I know why do I need on-chip fifo memory core? Can we just buffer the data in SDRAM?  4. do you mind to send me link about design examples that use fifo?  Appreciate your time, thank you very much.

[Altera_Forum]

You don't need a fifo core.... 

 The fifo core is only if you want to buffer avalon streaming data to avalon memory mapped data. I'm not sure how you are using the ADCs but my suspicion is that it is done through NIOS. Hence all you need to do is safe the sampled data into an array in C code (i.e. buffering in on-chip ram). The when you send out your uart information, you will be taking data out of that array.  In another one of your threads I posted a link to code that used uart interrupts. In that code, buffers are also used to store data for send out and collect incoming data. They were RxBuffer and TxBuffer. Look through that code, you should get an idea of how to use these buffer arrays.  If you want to use SDRAM, then you need to use IOWR and IORD functions to write your ADC data to specific SDRAM addresses, and then read the data out to send via uart. It's easier to use on-chip ram if you have the memory blocks.

[Altera_Forum]

--- Quote Start ---  You don't need a fifo core....  The fifo core is only if you want to buffer avalon streaming data to avalon memory mapped data. I'm not sure how you are using the ADCs but my suspicion is that it is done through NIOS. Hence all you need to do is safe the sampled data into an array in C code (i.e. buffering in on-chip ram). The when you send out your uart information, you will be taking data out of that array.  In another one of your threads I posted a link to code that used uart interrupts. In that code, buffers are also used to store data for send out and collect incoming data. They were RxBuffer and TxBuffer. Look through that code, you should get an idea of how to use these buffer arrays.  If you want to use SDRAM, then you need to use IOWR and IORD functions to write your ADC data to specific SDRAM addresses, and then read the data out to send via uart. It's easier to use on-chip ram if you have the memory blocks.  --- Quote End ---    Hi Krasner,  Thanks for your reply. OK, now I know there are two options, either buffering in on-chip ram or SDRAM  I have an issue where the rate the data is sent to serial port (50Hz) is way faster than the serial port can receive (8Hz). The incoming signal (50Hz) is from ADC receiver in VHDL block sent to the Nios. Basically, what I have is, data is sent from fpga vhdl block to NIos II system, Nios II system sends the data to serial port, Matlab access the serial port to real time plot the graph.   1. My question is, how by using say buffering in on-chip ram will help in this context? By doing so, I will still be losing some of the cycles? Am I right?  2. I just want to know if I understand the difference between the two, buffering in on-chip ram will require me to assign the data to an array (just like normal array assignment in C code?) and buffering in SDRAM would require me to use the iowr/iord because sdram is not built inside Nios, am I right?  3. What is the difference between "buffering in on-chip ram" and "assigning a data to the on-chip ram"?  4. I assume I do not use interrupt in this case right?  5. I did google and found this fifo example in C code, (http://coactionos.com/embedded%20design%20tips/2013/10/02/tips-a-fifo-buffer-implementation/ (http://coactionos.com/embedded%20design%20tips/2013/10/02/tips-a-fifo-buffer-implementation/)) Why people want to do the complicated fifo way if a normal array assignment in C can do the same??   Thank you in advance.

[Altera_Forum]

--- Quote Start ---  You don't need a fifo core....  The fifo core is only if you want to buffer avalon streaming data to avalon memory mapped data. I'm not sure how you are using the ADCs but my suspicion is that it is done through NIOS. Hence all you need to do is safe the sampled data into an array in C code (i.e. buffering in on-chip ram). The when you send out your uart information, you will be taking data out of that array.  In another one of your threads I posted a link to code that used uart interrupts. In that code, buffers are also used to store data for send out and collect incoming data. They were RxBuffer and TxBuffer. Look through that code, you should get an idea of how to use these buffer arrays.  If you want to use SDRAM, then you need to use IOWR and IORD functions to write your ADC data to specific SDRAM addresses, and then read the data out to send via uart. It's easier to use on-chip ram if you have the memory blocks.  --- Quote End ---    I dont know if this is feasible. What I am tempted to do, since the rate I can plot a graph is slower than the rate the incoming signal is read.  If I know the beginning of every incoming signal let say this point is indicated by a count=0, everytime I detect count=0, I know it is the beginning of each incoming signal, I keep track of how many cycles, let say, I only want to plot the graph every 10 cycles of the incoming signals, I plot cycle no.1, skip 10 cycles, plot cycle no. 11, skip cycle no.12 to 20, next plot cycle no. 21 etc ...in other words, it means I will lose some cycles in between which I am okay with this.  1. Do you think this method make any sense?  2. Do I still need buffering in this case?  3. How do I know how many cycles I need to skip? I assume it would depend on the incoming signal rate (50 Hz) and plot/receive rate (say 8 Hz), But I am not entirely clear about how to calculate...  The incoming signal (50 Hz) is from fpga vhdl, NIos system can read at 50 Mhz, but serial port receive rate or Matlab plot rate is 8 Hz.  Appreciate any input...thank you