I am implementing the bate metal part of an AMP (Linux + bare metal) application.
Before enabling caches I should set the SMP bit (because there are shared memory regions) and enable the SCU. I can find no means in HWLIB or SOCAL to do this. The HWLIB cache.c has defines for the SMP bit and read/write functions for the ACTRL register. But all these are just static inside the c module. No access from outside. Currently the only way to get the system running prperly is to copy code and implement my own jw_alt_cache.c. I expected the HWLIB to give me access to every register I might need. Or to wrap all necessary bits. Or did I overlook something? Joachim