Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12436 Discussions

How to set Speed: 100 Mbits full duplex instead oft Auto-negotiation on DE2-115 board

Honored Contributor II

Hello Friend's 


I have altera De2-115 board ....i want set speed: 100 mbits full duplex instead of auto-negotiation


How do i do this task ?. 


0 Kudos
4 Replies
Honored Contributor II

You'll need to write to the PHY's mdio registers. Register 0 is the control register, where you can disable autonegotiation and force 100Mbps speed. 


IEEE 802.3 Clause 22 contains the full details of this register, but here's the register contents: 

15 - reset 

14 - loopback 

13 - speed lsb 6,13 = 01 for 100mbps 

12 - aneg enable 

11 - power down 

10 - isolate 

9 - restart aneg 

8 - duplex, 1 = full, 0 = half 

7 - collision test 

6 - speed, msb 

5 - unidirectional enable 

4:0 - rsvd (0) 


For 100Mbps, full duplex: 

1010 0001 0000 0000 

or, 0xA100 



Are you positive you want to disable autoneg? If you connect the board to a device that is configured for auto-negotiation, it will parallel detect and you'll get a duplex mismatch. You could also configure the device to advertise 100Mbps only, but still use autonegotiation. You can do this via register 4 (and don't forget to hit the soft reset bit in register 0 after making any changes in register 4). If you have a 10/100/1000 PHY and you want to disable advertising for 1000BaseT, you'll also have to configure register 9.
Honored Contributor II

where is the location of PHY's mdio registers. & control register, or how could i write the mentioned value in these registers.

Honored Contributor II

Is it in file altera_avalon_tse.c ..? 


line no. 1573 (for auto-negotiation ) and  

line no 1830 (for speed)
Honored Contributor II

Once you have configured the TSE MAC with the correct PHY address (register mdio_addr0 or mdio_addr1, described on page 6-5 of the TSE's datasheet) the MDIO registers are directly mapped as TSE registers (see MDIO space 0 and MDIO space 1 on page 6-2). 

If you are using Altera's driver with the Interniche TCP/IP stack, after initialization the PHY address is already set up in mdio_addr1 so you can directly access the MDIO registers in MDIO space 1.