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Altera_Forum
Honored Contributor I
1,518 Views

How to transfer data array between HSP-FPGA & vice versa in CycloneV Soc (De1Soc)?

Hi, 

 

1) Is there a better way to transfer an array of data from HPS to FPGA and vice versa in Cyclone V Soc (or De1Soc board by Terasic)? I have used PIO and it is more suitable to send one data (or one uint32_t for example) at a time.  

2) Is there any component in Qsys that can handle data array? I prefer to use HPS-FPGA bridge rather than Lw_HPGA_FPGA bridge if the data rate is better. I appreciate if some example links are provided.  

3) What is the maximum speed of the Lw_HPGA_FPGA bridge can be used? 

4) What is the maximum speed of the HPGA_FPGA bridge? 

 

Thank you.
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4 Replies
Altera_Forum
Honored Contributor I
51 Views

1) 

a) You can use shared on chip ram if only FPGA have enough resources to accommodate array size. 

b) PIO is good, i use it alot, but sometimes i make custom PIO-like component, for example when i needed to export 383 bit wide digit. 

c) You can use Scatter-Getter DMA for transferring stream data to memory. HPS provides DRAM interface that allows FPGA part to write on HPS memory. If you are using linux, you can write a driver that allocates enough memory for your array and then transfer raw physical address of this chunk of memory to FPGA so it can read from and write to it. 

 

2) connect On-Chip ram to whatever bridge you want and make some experiments first. 

 

3,4) probably it is written somewhere in user manual, but ultimately TimeQuest Analyser will tell You maximum speed and it will always depend on what you connect to Your bridges. I have never needed more than 50 - 100MHz.
Altera_Forum
Honored Contributor I
51 Views

Thank you Settem. 

 

All I need to know is  

 

1) How to connect SDRAM (or FIFO or any memory) between FPGA and HPS ? 

2) How to read and write data from HPS ? 

3) How to read and write data from FPGA ? 

 

An example project containing this implementation would be very very helpful, or alteat documents on how to do it. 

 

Please consider me as an extremely new beginner for SoC, Qsys and accessing component between two subsystems.
Altera_Forum
Honored Contributor I
51 Views

Hi,  

 

Do you find any solution for your questions? I and my friend are beginners to this, and we have studied for our graduation project. However, we have not any solutions how to manage to connect them in plentiful documents. 

If anybody has an example project that communicate between HPS and FPGA for data transfer, please provide us info. Thank you.
Altera_Forum
Honored Contributor I
51 Views

The bridge example design here (targeting the Cyclone V SoC development board, but can be modified to run on other CVSoC board as well) should give you an idea on the transfer rate between the FPGA and HPS: 

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam...