How to use new component created in Qsys to vectorize/group together many signals

[Altera_Forum]

Hi, 

In the Qsys, I am using twelve input parallel ports (lets name them pio1 to pio12), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio12 from the nios ii system symbol so I can connect these pios to other blocks in my bdf.   My question is, how to vectorize these pio1 to pio12? Instead of seeing all twelve pios one line by one line coming out from the Nios system symbol, what should I do in order to group all these twelve pios so that I only see one instead of twelve? From the one pio that I see, I can name it pio[1..12][1..12], the first bracket means pio1 to pio12, the second bracket means bit1 to bit 12 because each parallel port has 12 bits.  I have created a new component in Qsys using this pio_helper.vhd file,    The pio_helper.vhdl file is as follows:  entity pio_helper is      port( pio1 : in std_logic_vector(11 downto 0); pio2 : in std_logic_vector(11 downto 0); pio3 : in std_logic_vector(11 downto 0); pio4 : in std_logic_vector(11 downto 0); pio5 : in std_logic_vector(11 downto 0); pio6 : in std_logic_vector(11 downto 0); pio7 : in std_logic_vector(11 downto 0); pio8 : in std_logic_vector(11 downto 0); pio9 : in std_logic_vector(11 downto 0); pio10 : in std_logic_vector(11 downto 0); pio11 : in std_logic_vector(11 downto 0); pio12 : in std_logic_vector(11 downto 0); piomerge : out std_logic_vector(143 downto 0) );   end pio_helper;   architecture behavior of pio_helper is     begin   piomerge(11 downto 0) <= pio1; piomerge(23 downto 12) <= pio2; piomerge(35 downto 24) <= pio3; piomerge(47 downto 36) <= pio4; piomerge(59 downto 48) <= pio5; piomerge(71 downto 60) <= pio6; piomerge(83 downto 72) <= pio7; piomerge(95 downto 84) <= pio8; piomerge(107 downto 96) <= pio9; piomerge(119 downto 108) <= pio10; piomerge(131 downto 120) <= pio11; piomerge(143 downto 132) <= pio12;   end behavior;    My question is, how do I access each pio1, pio2...pio12 etc in C code? since conduit component is not assigned base address? Thank you

[Altera_Forum]

You have to make your component compatible with the avalon bus. So your component will be an avalon slave.  

 http://www.alterawiki.com/wiki/qsys_lab_-_audio_frequency_spectrum_analyzer  This is a pretty detailed lab on how to use Qsys to create your own components and make them into avalon slaves.