Hello,I have the Opencores 10/100 Ethernet MAC which was updated and improved by Microtronix Datacom. I add it in my system under SOPC builder as the Avalon module and generate. But when I complie the system in QuartusII, the error occurs with "Info: Using design file igor_mac.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: igor_mac-europa Info: Found entity 1: igor_mac. Error: Node instance the_opencores_ethernet_mac instantiates undefined entity opencores_ethernet_mac. Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 402 warnings Error: Processing ended: Tue Dec 28 16:36:31 2004 Error: Elapsed time: 00:00:33. Error: Quartus II Full Compilation was unsuccessful. 1 error, 402 warnings." The Opencores 10/100 Ethernet MAC is written in Verilog, but is improved as a component of SOPC Builder. While I make my system in VHDL. What's the problem? If there is relationship between generated file-igor_mac.vhd and the module of Ethernet MAC. Thank you.
This is a problem with the Opencores.org EMAC component ptf file. When the SOPC system is specified as being created in VHDL, the Verilog source files don't get compied over. You can work around this by copying all the Verilog files from the Opencores.org EMAC component directory (<nios 2 directory>/components/opencores_ethernet_mac/) to your project directory.Dennis Scott Microtronix Datacom Ltd.
Should I add the "Interface to User Logic" and add the top-level file? But the top-level file(opencores_ethernet_mac.v) is the wishbone interface. How to assign the port type of it?
All of the port assignments are made in the class.ptf file that comes with the component. There is no need to add an additional interface.Dennis Scott Microtronix Datacom Ltd.
Hello,Comparing .ptf file of 91c111 component from Nios and Nios 2 I found two difference: class_version = "2.2"; Is_Ethernet_Mac = "1"; Do I need the same for OpenCores MAC .ptf file? What's the correct directory structure of C:\altera\kits\nios2\components for including OpenCores_Ethernet_MAC.c, OpenCores_Ethernet_MAC.h and OpenCores_Ethernet_MAC_regs.h files to use them with HAL and Nios 2? Thank you.
Hi, menottiFirst, I think there is no need to have the same class.ptf file. I have tried it with nios&nios2, and it can be compiled successfully in Verilog. But if you generate the system in VHDL under SOPC Builder, you should copy all .v file to your project directory, and you can compile them in Quartus. "class_version" is just a description. Second, the right structure is opencores_ethernet_mac\sdk\inc\igor.h opencores_ethernet_mac\sdk\lib\igor.c opencores_ethernet_mac\sdk\src\some examples. opencores_ethernet_mac\All the original Verilog files and class.ptf. Bye.
When you see a component folder that has a /sdk directory, then yes, that is for legacy SDK purposes.However as noted in other posts, Nir has posted an LWIP-compliant driver over in the "Post your own IP" area that works with LWIP and is not-legacy-SDK.