IP in component editor to conversion of block symbol file

[Mathiazhagan]

Hi all,

 In order to convert a IP in component editor of Platform designer to Block Symbol file in Quartus prime lite version 18.1

By default it has a clk_0 wizard by default in Platform designer, when i choose the Intel FIFO from component editor and i do all the customization required and when i add the FIFO in the design, It asks to connect to a clk and reset so i connected the clock of fifo to clk and reset of fifo to clk_reset, when i synthesized the design and created the block symbol file.

But the Block symbol file contains only the input as clk and reset, How to generate an block symbol file from an platform designer for an particular IP by customizing it. 

Waiting for your reply 

Thanks in advance 

[YEan]

Hi there,

The  block symbol file from Platform Designer will show the connection of your system only. If you want to view the block symbol of the customization IP, you can create it in the Quartus.

Thanks,

Ean

[Mathiazhagan]

Hi there,

Some of the IPs are only available in platform designer of Quartus, So if i want to use some IPs from platform designer as block symbol file in my project how to view the input and output signals of the customized IP.

Else share some tutorial to it which will be very much useful for me , Awaiting for your reply 

Thanks,

V.Mathiazhagan 

[YEan]

Hi V.Mathiazhagan,

You can try this workaround which is to export the signal. In the hierarchy menu, you will find your customize IP there, right click on the customize IP and select connections. The connections will show every signal available, select the signal and choose exported as:<name of the signal> , repeat this for every signal.  After you have completed, generate HDL again, the .bsf file should have all input and output signals of the customized IP now.

Thanks,

Ean

[YEan]

This was the video of exporting interfaces you may refer to https://www.youtube.com/watch?v=d43Pqc_IZpg&t=1340s .