Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

Igh EtherCAT master porting for Linux OS on CyconeV SoC

Altera_Forum
Honored Contributor II
1,067 Views

Hi, 

 

Does anyone could run well the Igh EtherCAT master for linux-RT of Cyclone V ? 

 

I got the linux-socfpga.git for downloading Linux-3.10-ltsi-rt. 

I already put the EtherCAT module and application on the Linux-RT Helio board for Cyclone V. 

It could run well as communication cycle as 10 ms. 

 

And the Ethernet port will block when I use 1ms transmit rate. 

It seems that the delay of ethernet transmit/receive function is too long. 

 

Has anyone also verify the situation or anyone could point out the delay issue?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
261 Views

 

--- Quote Start ---  

Hi, 

 

Does anyone could run well the Igh EtherCAT master for linux-RT of Cyclone V ? 

 

I got the linux-socfpga.git for downloading Linux-3.10-ltsi-rt. 

I already put the EtherCAT module and application on the Linux-RT Helio board for Cyclone V. 

It could run well as communication cycle as 10 ms. 

 

And the Ethernet port will block when I use 1ms transmit rate. 

It seems that the delay of ethernet transmit/receive function is too long. 

 

Has anyone also verify the situation or anyone could point out the delay issue? 

--- Quote End ---  

 

 

 

 

Hi, Were you able to successfully use the TSE IP core for Ethercat master? How is the performance?
Reply