Importing IP into SPOC builder

[Altera_Forum]

Hi all, 

I'm currently working on building an sopc builder and using on cyclone III target device. I have written a simple counter program to glow the LED's to familiarize myself with SOPC builder. I imported my IP into the component editor, added the HDL file and have to connect signals in my design to an interface and signal type. My signals are  1. Clk (input) 2.reset (input)  3.Display (output)  So i connected my clk to a clock_sink. But none of the other interfaces and signal types available seem to match my requirement, because I'm driving reset externally using a switch. And outputs are connected to LED's. I tried using conduit interface and export the signals but that does not work.  Help needed. Thank you.

[Altera_Forum]

Use conduit interfaces. It does work. 

You're welcome.

[Altera_Forum]

If i use conduit interface, then is there need for me to include Nios processor and other components as the processor has no control over the signals..

[Altera_Forum]

No, you can build SOPC system without any Nios processor.

[Altera_Forum]

Without nios processor, during compilation i get an error saying cannot synthesize top module as it has nothing.

[Altera_Forum]

Could you give the exact error message? I don't recall any error message from Quartus that would say that. 

Does SOPC builder say anything during generation? Does the generated SOPC component has all the ports that you need? Did you instantiate it correctly in your top level file?

[Altera_Forum]

Hi, I'm beginner.

[Altera_Forum]

re: could you give the exact error message? i don't recall any error message from quartus that would say that. 

does sopc builder say anything during generation? does the generated sopc component has all the ports that you need? did you instantiate it correctly in your top level file?  1.When i don't use Nios processor and generate SOPC, there are no error messages during generation. 2. But the HDL component file generated by the builder does not have the signals which are present in my design. 3. When i make this HDL component file generated, as the top module and compile using quartus, the following error is thrown  "Error (12061) : Can't synthesize current design -- Top partition does not contain any logic.", Which is obvious because the HDL file has no signals. But when i include the Nios Processor the generated HDL component file has the signals which are in my design and compiles without any error.

[Altera_Forum]

Did you add any other logic to the Nios CPU in the SOPC builder project? When compiling without the Nios CPU, what messages to you have form the SOPC builder generation? 

I've never done such a simple system with SOPC builder, maybe it's expecting at least an Avalon interface somewhere... By the way you can still use a standard reset interface for your reset signal, even if you are using an external switch as reset. It will automatically create a reset input on the generated system.

[Altera_Forum]

Yes,Nios requires at least one avalon interface to communicate with my design. So i added few Avalon slave signals (which i don't need but its required for Avalon interface between Nios and My design) such as read_en,write_en,read,write,address. The HDL component file generated now has the signals that are present in my design which i have exported using the conduit interface. Then i instantiated this HDL component file in a top module and passed the Clk and reset signals. And yes thanks for the tip i used the same reset generated by system. The system works as expected. 

Thank you.