There could be several reasons. First the access from the NIOS CPU to the registers you write with IOWR could itself be slow, for example if you are using different clock domains without a clock crossing pipeline bridge. In this case the synchronization logic automatically added between the master and the slave is rather slow.
Also the access from the NIOS CPU to the program memory could be slow too. In that case it can take several clock cycles for the CPU to read the second IOWR instruction.
You could make it quicker by using memory caches, if they aren't enabled. An instruction cache will make the loading of the second IOWR instruction faster. If you have a data cache, then you can write your registers using regular pointers instead of IOWR. Then the values will be written in the data cache, and once you have written everything, trigger a cache flush and ell the registers will be written in a burst.
