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Honored Contributor I
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Instantiate a Custom Register Map interworking with HPS and PCie Avalon MM

Hi to all, I've a bunch of registers managed with our internal bus protocol, so we should insert a Avalon MM bridge to translate our protocol .(It is a propietary bus protocol used by our company in several FPGA projects)  

I've a question , the instantiation of this map of registers could be done with instantiation in a custom Qsys IP ?  

Could you give me an example of interfacing HPS with an custom IP in logic (it is a bank of several registers, about 2000 registers with different addresses not contigous), I need an example similar with a bunch of registers. 

Also this interface should be accessed by Hard Pcie Avalon MM. So we have 2 masters that control the registers, the HPS and Pcie , this arbitration is done by Qsys interconnect , of course . 

 

Best Regards
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