Intel HLS example reports - Page 2

Altera_Forum · ‎01-24-2018

Hello,

I am new to the concept of HLS. I am using Intel HLS and going to start with the examples that come with the installation of Quartus prime edition.

Can anyone of you share the successful project report files generated after testing any of those examples ? The examples are Counter, image_downsample,interp_decim_filter,QRD and YUV2RGB. Anyone who has tried with one of these examples, it would be great if you can attach the project files post synthesis in this thread ....

Will be thankful

Altera_Forum · ‎02-12-2018

Based on this modified code of yours now I am trying to use ac data type fixed . The two inputs are unsigned ac_ufixed<11,1>. The output is unsigned ac_ufixed<28,8>. The accumlator is ac_ufixed<28,8>, a_reg and b_reg as ac_ufixed<11,1> , sub as ac_fixed<12,2>, sub2 as ac_ufixed<21,1> . How can I define the test bench for this particular component ? Can you please help me particularly for the test bench of this component ? Below is my code snippet (component).... Thanks !

void diff_sq_acc( ac_ufixed<11,1> a[N], ac_ufixed<11,1> b[N], ac_ufixed<28,8> *dout)

{

unsigned char i;

ac_ufixed<28,8> acc= 0;

ac_ufixed<11,1> a_reg, b_reg;

ac_fixed<12,2> sub;

ac_ufixed<21,1> sub2 ;

for(i=0; i<N; i++)

{

# pragma HLS PIPELINE II=1

a_reg = a;

b_reg = b;

sub = a_reg - b_reg;

sub2 = sub*sub;

acc += sub2;

}

*dout = acc;

}

Altera_Forum · ‎02-13-2018

Dear Anand,

can you please help me with the proposed code of mine in which i have used fixed data types ? I wll be grateful.

Altera_Forum · ‎02-14-2018

Hi,

You can refer following code and i have not optimized it.

#include "HLS/hls.h"
# include <stdio.h>
# include "HLS/ac_int.h"
# include "HLS/ac_fixed.h"
# include "HLS/extendedmath.h"
# include "HLS/math.h"
typedef ac_fixed<11, 1, false> fixed_11_1_t;
typedef ac_fixed<28,8,false> fixed_28_8_t;
typedef ac_fixed<12,2,true> fixed_12_2_t;
typedef ac_fixed<21,1,false> fixed_21_1_t;
# define N 2
component void dut(fixed_11_1_t a, fixed_11_1_t b, fixed_28_8_t *dout)
{
unsigned int i;
fixed_28_8_t acc= 0;
fixed_11_1_t a_reg, b_reg;
fixed_12_2_t sub;
fixed_21_1_t sub2;
for(i=0; i<N; i++)
{
a_reg = a;
b_reg = b;
sub = a_reg - b_reg;
sub2 = sub*sub;
acc += sub2;
}
*dout = acc;
  
 }
int main() {
	fixed_28_8_t z;
	fixed_28_8_t ip = &z;
	fixed_11_1_t x={128.1,128.1};
	fixed_11_1_t y={128.1,128.1};
  dut(x,y,&z);
  printf("Test ecxecuted\n");
getchar();
  return 0;
}

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎02-14-2018

thanks Anand...........can you please attach the running code and report in the attachment ? i will be grateful.

Altera_Forum · ‎02-15-2018

Hi,

https://drive.google.com/open?id=1ee_imbjtkoko-ou4vxlp_oghbu85ccd3

You may see the warning "Compiler Warning: Auto-unrolled loop at xxxx/.cpp" it is because loop size which to be changed.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎02-15-2018

thanks Anand..........and the simulation is done through Modelsim ?

Altera_Forum · ‎02-15-2018

Dear Anand,

You have been a great help..... Just one last thing. I have a code from Xilinx repository. I have synthesized in Vivado. Can you please help me in that code also. I am trying to make comparative report . It is a sub optimal code and it should remain sub optimal.... It is in C++ and uses arbitrary precise data types. Does not need any changes. Below is the link......it is cordic square root........Please let me know...

https://github.com/xilinx/hlx_examples/tree/master/math/sqrt_cordic