Trying to interface a custom SDRAM component with 2 FIFO buffers (not created by me) with the NIOS II so that we can do image processing on a video stream.The verilog file was provided by Terasic within their DE2-115 TRDB-D5M camera example. When interfacing the NIOS II with the SDRAM in qsys, we're having trouble selecting the correct signal types as well as interface, and can't proceed to our next step. Could anyone help us choose the correct signal types and complete our hardware interface?
Try creating an ordinary memory interface with the standard Altera controller. As part of the process a TCL file is created with the settings you are talking about. Get the standard interface working and passing memory tests first in a fresh project. You should then be able to use the settings in the TCL file for guidance on what to set in your real project.