Dear All,I would like to start by saying I am quite new to HDL, FPGAs and the IDE. I've worked through a few digital design examples entirely but I feel like I want to tackle a larger problem using a the nios ii processor. Apologies for my noobiness in advance... I have a small verilog module which I have written and compiles, however I would like to take the information from the module (two numbers in a 32-bit register each) and transfer it to a LCD/PC etc. After some thinking I think would be easiest to interface the verilog module with a nios ii processor as the verilog can be left to handle the high speed digital side, and the nios ii can be left to leisurely access and send/receive data with a PC. I've managed to work through a couple of very basic hello world nios ii designs, but none interface with a verilog module. However, I cannot seem to find any clear literature/guides on how I would go about starting with my verilog module and connecting it to my nios ii. Could anyone point me to any suitable resources, or offer some direct assistance? Is it just a case of creating a couple of parallel I/O's and then instantiating them in my top-level entity (where my current verilog file sits)? Or do I need to create my own qsys component? fwiw I'm using Quartus Prime Lite Edition with a Cyclone IV. Thanks in advance.
Hi,--- Quote Start --- Is it just a case of creating a couple of parallel I/O's and then instantiating them in my top-level entity (where my current verilog file sits)? Or do I need to create my own qsys component? --- Quote End --- Yes, create a custom component and try to use. All required information is in below like. ftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/making_qsys_components.pdf Let me know if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Hi, apologies for the long delay.I've worked my way as far through the process as I can, though I as I'm still new there are many things I am not understanding. :oops: When I am generating my custom component, I get a wide variety of errors and warnings, and I'm not entirely sure as to what I need to change my ios to, in order to remove these. Can I have any suggestions or recommend any documentation which might help me decide? If you don't mind, I'd like to clarify what I'm intending to do here. I've created a verilog file which has some connections to external hardware (in this case, inbitstream, outbitstream, ledstatus and clk). The others I'd like to use with a NIOS II processor (incorrectbits, totalbits, start, and reset), as I will use the processor to send information to a PC for collection. My intention is to simply use the processor to 'start' the verilog module, by changing the state of 'start', then at some point later in time, it will change the state of 'start', and read the contents of incorrectbits and totalbits. Does this seem feasible in this scenario, or am I making some fundamental mistakes in my approach? I've attached a copy of my screen which may clarify, if not please ask and I will try my best to explain better. :) edit, I cannot attach a high enough res image to be of use, a sample can be found here: https://s15.postimg.cc/di9etn7rf/avaloninterface.png https://alteraforum.com/forum/attachment.php?attachmentid=15458&stc=1 Regards. https://alteraforum.com/forum/attachment.php?attachmentid=15457&stc=1
battersea, the simplest method to connect to your custom built module is using PIO in the Qsys system. In that case you will communicate with your designed peripheral as if it is an "external peripheral" to your Qsys system and you are linking with it using general purpose I/O ports from a processor (basically how microcontrollers connect with on board peripherals).If you already know how to use the Qsys PIO peripheral, you can create a few in your Qsys system, connect their exported conduit to your custom written block and then toggle the signals or read them as required via the PIO. If your custom block only requires basic I/O then using PIO will be simpler for you at this stage.
XAUI, that is the perfect response, thanks so much for the easy clarification! Just to be 100% sure, when you say"connect their exported conduit" This is still enabling the "external_connection" Conduit in the System Contents map, correct? Just instead of assigning the conduit to a pin in pin planner, I will instantiate it to a sub module? Many thanks again, it is really appreciated. EDIT: To answer my own question, yes, still enable external_connection, many thanks again XAUI. :)