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Interfacing of Nios-II and Triple Speed Ethernet in Qsys in MII Mode

Altera_Forum
Honored Contributor II
1,030 Views

Hi, 

 

In our design we migrate communication to ethernet port. We have Cyclone-IV (E) EP4CE55F484 FPGA with DP83848C Ethernet PHY. We try to interfacing Ethernet PHY with Nios-II. We are using Triple Speed Ethernet in Qsys where we configure TSE in MII Mode. We are facing problem while interfacing Nios-II and TSE IP through Avalon-ST. In Qsys library there are different types of Avalon-ST is given in Bridges and Adapters, so which Avalon ST bridge should i connect? 

 

So please somebody guide us to how we connect the Nios-II and TSE in MII Mode? 

 

Thanks in Advance 

 

Piyush Mahajan.
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3 Replies
Altera_Forum
Honored Contributor II
147 Views

traditionally the TSE is used with two DMAs to read and write packets. The Altera driver used with uCOS and the Nichestack expects two SGDMAs. There is a standard example design on the Altera web site that shows how they are connected here: http://www.altera.com/support/examples/nios2/exm-net-std-de.html

Altera_Forum
Honored Contributor II
147 Views

 

--- Quote Start ---  

traditionally the TSE is used with two DMAs to read and write packets. The Altera driver used with uCOS and the Nichestack expects two SGDMAs. There is a standard example design on the Altera web site that shows how they are connected here: http://www.altera.com/support/examples/nios2/exm-net-std-de.html 

--- Quote End ---  

 

 

 

Thanks, i already gone through this design. But that design having TSE which is configured as 10/100/1000MB ETHERNET MAC and RGMII Mode. 

 

As we want configure TSE as 10/100MB SMALL MAC and MII Mode. So SGDMA will support MII Mode (10/100MB SMALL MAC)? 

 

Waiting for your reply. 

 

Piyush Mahajan
Altera_Forum
Honored Contributor II
147 Views

It is the same and the same setup should work with a small 10/100 mac. The connection between the TSE and the DMA are standard Avalon Stream interfaces, and don't depend on the actual Ethernet protocol. The only things you must set in the TSE are to define the interfaces as 32 bits, have fifos and align the packet headers on 32 bits (this is actually a requirement for the Interniche drivers).

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