Depends on what you mean by atomic. If you mean whether a 32-bit access will become corrupted by the other CPU then answer is no if they perform aligned 32-bit accesses. But if you are looking to perform a mutually exclusive access where you lock down a memory location (mutex) the only HPS memory that supports this is the SDRAM controller and Nios II doesn't have to ability to generate AXI traffic to perform a mutex access. You could add this ability fairly easy but making a custom instruction that exposes an AXI master to perform the mutex access into the HPS SDRAM though.
By the way, I don't recommend using your email address as your account name, if you want to change it to avoid getting spammed send me a private message with what you want me to change your user account name to.
