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Altera_Forum
Honored Contributor I
770 Views

Issue with polling in Nios

Hi, 

 

I've got a custom component that produces some results from time to time, I want Nios processor to monitor the process by polling and whenever a result is produced, it is written to a external memory. I'm new to Nios and I've got some questions: 

 

1. I know that I need a flag bit and whenever the result is available the flag should be raised, and I should keep the result available as long as the flag is high however I don't know when I can lower the flag and change the content in the result bits. 

 

This leads to the next question 

 

2. If the time gap between the results produced is very small, should I still use polling? Is there any chance a part of the results are missed by the Nios? 

 

Thanks a lot!
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10 Replies
Altera_Forum
Honored Contributor I
55 Views

Hi 

 

1. whenever the result is available the flag should be raised.... and after the results is read, lower the flag : your component set the flag when results are available and Nios II reading operation clear the flag. 

 

2. You should read signals that are asynchronous or that may change their values within a reading operation. So Keep the results until they are read is a good solution.
Altera_Forum
Honored Contributor I
55 Views

It is more usual to use a 'write 1 to clear' action on the status register. 

That way you can to diagnostic reads without clearing the data.
Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

Hi 

 

1. whenever the result is available the flag should be raised.... and after the results is read, lower the flag : your component set the flag when results are available and Nios II reading operation clear the flag. 

 

2. You should read signals that are asynchronous or that may change their values within a reading operation. So Keep the results until they are read is a good solution. 

--- Quote End ---  

 

 

thanks, in your answer to my second question did you want to say 'you should not read.....'?  

 

Then what if the time gap between two consecutive results are very small? Say the results are produced every two clock cycles, one solution I can think of is to use a FIFO and do batch transition whenever necessary, what is the common solution in this case? 

 

thanks!
Altera_Forum
Honored Contributor I
55 Views

Hi, 

 

you can either use a FIFO and a counter or throw a software interrurpt everytime new data is generated. It depends on your application. If the data is deterministc, you'll need interrupts
Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

thanks, in your answer to my second question did you want to say 'you should not read.....'?  

--- Quote End ---  

 

Yes, indeed ! :-) 

 

If your results are synchronous, then you can read at any (obviously synchronous) time. 

 

Do you want to read ALL the results ? OR do you want to read results sometimes ? That is the question. 

In the first case, you may need a FIFO 

In the second case, you just need to read. you have to read data that don't change when you read (of course). Use synchronous design and/or a register that keeps a stable "result" when being read. 

 

interrupts or polling mode is a choice : 

In polling mode, you have to read time to time even if there is no new results. Need a flag somewhere.  

You may miss results if your reading loop is not fast enough to read the results. 

Question of gap between results is more a timing question. 

 

In interrupt mode, your main program will be interrupted in order to treat the interruption. Need no flag because you assert the interruption. 

 

DO your results come from an external component ? In this case, you should resynchronize (by using at least 2 cascaded D Flip Flop) to avoid metastablilty (I experienced that).
Altera_Forum
Honored Contributor I
55 Views

For your second question, if you can tolerate latency then I think a FIFO and interrupts will probably be your best bet (I'm not certain because I don't know exactly what you are doing). 

 

Say you are moving data at a high rate from custom logic into the Nios II core, you would want the data buffered into a FIFO that supports a 'fill level'. A fill level can be something like the FIFO being half full, or 64 words buffered, etc... Once the fill level is hit because you choose what the fill level is set to you can have the CPU rapidly read data to drain the FIFO contents. The tricky part is making sure that you handle corner cases like Nios II emptying the FIFO just as fast as it's filling and potentially an interrupt being missed as a result. That's easily solved but that's the sort of thing you need to remember when you have events in your system. 

 

Often when the data rate becomes too high you rely on DMA engines that will move the data into memory so that Nios II can access it directly, and the DMA engine would be responsible for letting the CPU know when the data has been stored to memory.
Altera_Forum
Honored Contributor I
55 Views

Hello! 

Is it a correct style to use polling for NIOS II? 

 

unsigned int data=0; 

while ( data == 0x00 ) 

data = IORD_ALTERA_AVALON_PIO_DATA (PIO_0_BASE) && 0x01;  

// polling has finished after reaching data == 0x01
Altera_Forum
Honored Contributor I
55 Views

&& is a logical AND, I think you are doing a bit mask so I would use one & instead. Also I would declare data as a volatile variable to make sure the compiler doesn't attempt to optimize it away.

Altera_Forum
Honored Contributor I
55 Views

 

--- Quote Start ---  

&& is a logical AND, I think you are doing a bit mask so I would use one & instead.  

--- Quote End ---  

 

Yes! I new it but confused one & and two & ((( 

 

--- Quote Start ---  

Also I would declare data as a volatile variable to make sure the compiler doesn't attempt to optimize it away. 

--- Quote End ---  

 

I didn't know about this, so I thank You even more! 

Here I just found an example with volatile variable to be used with polling. 

It confirms Your words! 

http://www.seomastering.com/wiki/volatile_variable
Altera_Forum
Honored Contributor I
55 Views

If the compiler was optimizing out 'data' then it most likely turned the while loop into a simple if statement. The justification for this is without volatile the compiler will assume that reading the location multiple times will result in the same data being read and the optimization is to turn it into a single read. Volatile lets the compiler know that something outside of the executable execution will modify that location, it's common to use volatile when accessing hardware or shared memory locations.

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