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Altera_Forum
Honored Contributor I
967 Views

Jam STAPL Byte-Code Player TCK Speed Slow

I am using a the Jam STAPL Byte-Code Player Version 2.2 code provided by Altera (found here https://www.altera.com/download/legacy/jam/dnl-byte_code_player.jsp) and some custom software to configure a Cyclone V device. However I am having a lot of trouble configuring it at a reasonable speed. It takes about 15 minutes to configure the device! I have a feeling that TCK is the cuplrit. The TCK signal that is being produced is approx 34.5kHz. I believe the Cyclone V can handle a much faster TCK but I do not know what is causing this to be so slow.  

 

Does anyone have an idea what might be causing this? Is there a setting I am missing in Quartus II v13.1 when building the jbc file? 

 

Any help would be much appreciated! Thanks!
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Altera_Forum
Honored Contributor I
66 Views

So looking at the code located in the jbistub.c file I found this; 

 

void calibrate_delay(void) { int sample = 0; int count = 0; DWORD tick_count1 = 0L; DWORD tick_count2 = 0L; one_ms_delay = 0L; # if PORT == WINDOWS || PORT == DOS for (sample = 0; sample < DELAY_SAMPLES; ++sample) { count = 0; tick_count1 = get_tick_count(); while ((tick_count2 = get_tick_count()) == tick_count1) {}; do { delay_loop(DELAY_CHECK_LOOPS); count++; } while ((tick_count1 = get_tick_count()) == tick_count2); one_ms_delay += ((DELAY_CHECK_LOOPS * (DWORD)count) / (tick_count1 - tick_count2)); } one_ms_delay /= DELAY_SAMPLES; # else /* This is system-dependent! Update this number for target system */ one_ms_delay = 1000L; # endif } // end calibrate_delay() 

 

It looks like its trying to count the amount a clock ticks in between a certain time period and then calculate how many clock ticks it would take for 1 milisecond to occur. However I am not sure if this is being done correctly.  

 

Another thing to note is that I am using a Win7 Pro 64-bit machine with a 4 core CPU. I have noticted that when running the jam player code that exactly 25% CPU is being used (or one core). I am Not sure if that is related to the issue or not but thought it be worth mentioning.
Altera_Forum
Honored Contributor I
66 Views

So now I am confused even more as to why I am not getting TCK at a faster speed. When I make the JBC file it states right there that TCK frequency is 10MHz! Why is it when I scope it, it shows ~35kHz???? 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8815  

 

I keep on coming back to how clocks are calculated and have a feeling that is what is causing this issue but I am not big on software programming to find/understand the issue. Any help? Anyone????
Altera_Forum
Honored Contributor I
66 Views

So now I noticed that the TCLK was going low twice as long as it was going high. I found that in the code and commented it out (not sure why it was there) and that sped up the clk to 50kHz from 33kHz. However, it still takes about 11 min to configure the FPGA and about 8 min to program the EEPROM device. 

 

Could it be taking so long because of the size on the Cyclone V device?
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