Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

K4H561638N-LCC ddr controller parameters (xml)

Honored Contributor II

Anyone knows how to fill ddr controller timing parameters from the datasheet? 

Specifically i need K4H561638N-LCC parameters, I think they are similar to the K4H561638F-TCC parameteres. Have I need to use the min time for the parameters?  



Many thanks. 


0 Kudos
1 Reply
Honored Contributor II

There should be different sets of timing numbers depending on the frequency. If you take the conservative "loose" approach (choose highest timing values) the interface will continue to work but it might not give you the best performance possible. You could make different configurations for different clock frequencies while you are developing in case you don't have your memory clock speed set in stone yet.