According to NIOS II 5.0 errata, LAN91C111 doesn't handle properly bursts from a DMA, because ARDY signal is not monitored.Could some of you workaround this problem? I need to send data from SDRAM to LAN91C111 using DMA and vice-versa. Best Regards, Celso
Hi Celso,After much investigation this is being corrected in 5.0service pack 1 by changing timing to the ethernet chip. Due to a variety of factors it made more sense, believe it or not, to follow worst-case timing parameters to the 91c111 than use its ARDY signal; basically, there was no way to do any sort of burst to it without the ARDY dropping. As a result we are adjusting the timing parameters to the 91c111, stored in its class.ptf file. You can change this yourself, if you'd like, by first closing SOPC BUilder and then editing the altera/kits/nios2/components/altera_avalon_lan91c111/class.ptf file and searching for/replacing the following lines: Read_Wait_States = "175ns"; Write_Wait_States = "175ns"; Setup_Time = "10ns"; Hold_Time = "5ns"; After this, save the file, re-open SOPC Builder, re-open any designs with Ethernet, delete the ethernet component, re-add it from the list of peripherals, and re-generate the system. It is, sadly, true that this will also reduce throughput from the CPU when it talks to ethernet, but to fully comply with the device's timing specifications we didn't have much choice. The bus throughput to/from the ethernet chip is still well over 100Mbit/second though, when using a 32-bit data bus, with the new timing settings.
So if I understand it right, the increased wait states will slow down the single-cycle access, but allow DMA xfers?If you aren't using DMA, does it make sense to stick with the old settings?