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Altera_Forum
Honored Contributor I
760 Views

LCD Master interface and NIOS Pipeline issue

I all, 

 

I've a SoC based on a NIOSII/f and a LCD controller with a Master interface for accessing the memories in order to update the display content. 

 

Here is the function I use to "clear/fill-up with a color the display. 

 

void Pe_lcdClear(UInt16 background) { pe_lcdBackground.RGB = background; pe_lcdStartDma((Pixel*)&pe_lcdBackground, LCD_W*LCD_H, False); //False: do not increment the source address }  

 

 

The global variable "pe_lcdBackground" is located in to the onchip_Ram. 

 

This is the code flow: 

 

Pe_lcdClear(0x0000); //Black Background Pe_lcdClear(0xFFFF); //White Background Pe_lcdClear(0xFFFF); //White Background  

 

On the display I see the following: 

  • black 

  • black 

  • white 

 

 

The first time it seems to work properly (desired black, drawn black). But is actually only because the "pe_lcdBackground" is 0 initialized. 

 

The value I write into the variable is not taken into account for the successive start of the DMA, it seems that the DMA sees the old value written in the memory. 

By putting a break-point after assigning "pe_lcdBackground.RGB = background" and by writing/using an expression involving the variable pe_lcdBackground, makes the issue disappear.  

That means: the desired vale is properly drawn on the display. 

 

So, could it be a pipeline issue? So that the NIOS does not write the memory before the DMA starts and "lock" the memory access? 

Does anyone knows as an input to fix/workaround this?? 

 

Many thanks in advance! 

 

Regards
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1 Reply
Altera_Forum
Honored Contributor I
32 Views

It was not a pipeling problem, it was a cache problem! 

 

I've solved it by calling:  

alt_dcache_flush_all(); 

 

before calling the dma start function.
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