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Linker.x incorrect .exception address

Altera_Forum
Honored Contributor II
839 Views

Hello, 

 

This was posted in another forum by mistake. 

 

I have a NIOSII processor in a system with DDR2 ram, an external flash, and a utram. In the SOPC NIOS GUI I've set the exception address for the NIOS at 0x0c000120 (the utram address). This should ensure that NIOSII uses this memory space for program execution, correct? 

 

The following is what I see in the linker.x file which has all the correct memory components: 

 

memory 

{ 

ext_flash : origin = 0x0, length = 67108864 

utram32bit_interface_0 : origin = 0x4800000, length = 8388608 

ddr2_sdram : origin = 0x8000000, length = 67108864 

utram32bit_controller_0_before_exception : origin = 0xc000000, length = 288 

utram32bit_controller_0 : origin = 0xc000120, length = 8388320 

reset : origin = 0xe000000, length = 32 

boot_rom : origin = 0xe000020, length = 8160 

descriptor_memory : origin = 0x1a000000, length = 4096 

} 

/* define symbols for each memory base-address */ 

__alt_mem_ext_flash = 0x0; 

__alt_mem_utram32bit_interface_0 = 0x4800000; 

__alt_mem_ddr2_sdram = 0x8000000; 

__alt_mem_utram32bit_controller_0 = 0xc000000; 

__alt_mem_boot_rom = 0xe000000; 

__alt_mem_descriptor_memory = 0x1a000000; 

 

 

The above appears to ok, but, when I look at the .exceptions section: 

 

sections 

{ 

.entry : 

{ 

keep (*(.entry)) 

} > reset 

.exceptions : at ( 0x8000000 ) 

{ 

 

The reference is to the DDR2 memory space... and, when I program the NIOS, it tried to execute from 0x8000000 and fails. 

 

However, when I manually edit the .exceptions : AT (0x8000000) to AT (0xC000120), the processor comes up and works correctly. 

 

It seems like the linker.x file (an autogenerated file) is not being updated per the SOPC settings... Any ideas how to fix this? I don't want to have to modify this fioe manually for every build. 

 

Thanks, 

Mike
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