Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

Logic level of output pins at power-up and power-down

Altera_Forum
Honored Contributor II
1,044 Views

Can anybody tell me how to set the logic level of output pins to GND during power-up and power-down? Many thanks.

0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
90 Views

 

--- Quote Start ---  

Can anybody tell me how to set the logic level of output pins to GND during power-up and power-down? Many thanks. 

--- Quote End ---  

 

 

You need to use an external resistor to pull-down the pins you want at logic low level. Altera FPGAs have on-chip weak pull-ups, but not pull-downs. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor II
90 Views

Thanks.  

 

Unfortunately, I am unable to change anything on my target board.
Altera_Forum
Honored Contributor II
90 Views

No...i have to keep streming the pic to the screen

Reply