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Altera_Forum
Honored Contributor I
802 Views

MAX10 ALTPLL: What to do with areset?

Hi, 

 

The wizard has a check box to enable or disable this areset pin but checked or not this pin keeps showing up in qsys and qsys complaints that it needs to be exported. It shows up in the pin planner too. The documentation says: 

 

"The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals."  

 

Does it matter if I erase it from the pin planner or leave it unconnected after I uncheck the box? Why does it show up after the box is unchecked? This is confusing for me as I'm new to fpga. 

 

Thanks
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2 Replies
Altera_Forum
Honored Contributor I
34 Views

If your PLL gets configured only once, at power-up for example, then I would just tie areset to its de-asserted state (low I believe). If you plan on dynamically reconfiguring the PLL, then it's advisable to pulse the reset after reconfiguration.

Altera_Forum
Honored Contributor I
34 Views

It is recommended to have the areset enabled so that you could reset your PLL when it lose lock or after dynamic reconfiguration.

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