Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Beginner
22 Views

MAX10 Nios2/f and dual-port RAM

Jump to solution

I implemented some of the M9K memory blocks in Nios2 as dual port RAM for exchanging data with the outside.
Both memory width is 16bit.
There was no problem when using Nios2/e as the CPU, but after changing the CPU to Nios2/f, I could not read data from the outside.
Please let me know if you have any suggestions on how to deal with this problem, or when changing from Nios2/e to Nios2/f.


Software
#define S_AREA (ONCHIP_MEMORY2_1_BASE + 0x100)
#define SSTATUS (*( volatile uint16_t * )( S_AREA + 0 ))

SSTATUS = 0x002f;

*Uses Google Translate

 

Original

外部とのデータのやり取りのためにNios2にM9KメモリブロックのいくつかをデュアルポートRAMとして実装しました。
メモリ幅は双方とも16bitとしています。
CPUとしてNios2/eを使用しているときは問題無かったのですが、CPUをNios2/fに変更したら外部からデータが読み出せなくなりました。
この問題に対処する方法、またはNios2/eからNios2/fに変更する際の注意点などありましたらご教示ください。

0 Kudos

Accepted Solutions
Highlighted
Beginner
9 Views

Re: MAX10 Nios2/f and dual-port RAM

Jump to solution
If the CPU cache memory is disabled, the value written in the dual port RAM can be read.
Specifically, in Qsys, all of Instruction Cache, Flash Accelerator, and Data Cache in the Caches and Memory Interface tab of Nios2 Processor are set to NON. It may be fine to disable only the Data Cache, but since I achieved the purpose, I have not checked with other enabled.
 
 

View solution in original post

0 Kudos
1 Reply
Highlighted
Beginner
10 Views

Re: MAX10 Nios2/f and dual-port RAM

Jump to solution
If the CPU cache memory is disabled, the value written in the dual port RAM can be read.
Specifically, in Qsys, all of Instruction Cache, Flash Accelerator, and Data Cache in the Caches and Memory Interface tab of Nios2 Processor are set to NON. It may be fine to disable only the Data Cache, but since I achieved the purpose, I have not checked with other enabled.
 
 

View solution in original post

0 Kudos