Hello all,I am trying to access registers in a device communicating with my CycloneIV through MDIO clause 22. I added the "Ethernet MDIO" module in my QSys design along with Nios. My question is: how do I access the registers of the MDIO interface (OP, PRTAD, DEVAD, REGAD)? I can't find them in BSP directory.
Update:The registers are in the memory , their address is in the on-chip memory at mdio module's base address + the offset (0x20) However, I am not able to communicate with my device since the operation code 10 (read in Clause 22) is not supported in the Altera module, which is actually built for Clause 45. Therefore, I am switching to VHDL code for this task.
The MDIO module from Altera only supports clause 45, as you discovered. To use clause 22, you will need either to do it yourself in VHDL, or use a complete MAC. The Triple Speed Ethernet MAC from Altera includes a clause 22 MDIO module. Now that said it could be a bit overkill to put a full MAC component just to use the MDIO part ;)
It could be worth a try but I think that if you used the TSE and leave all the Ethernet signals unconnected, a good part of the MAC would be optimized away and removed by the synthesizer. It just leaves another problem, it's that you need a license for the TSE IP, and it is probably not worth paying the full license just for the MDIO part.Did you have a look at Opencores.org for an MDIO component? They may have something you can use.
I'm a student, full licence of an IP core is out of the questionThey do have it at opencores, but it's also in a Ethernet core and I don't really need all these signals. I will write my own version, short and simple Cheers
Can anyone in this discussion tell me if a mdio slave device can communicate back with the STA and if so how. Looking at the clause 45 spec, it looks like this is not possible.
I have just discovered this also - no Clause 22 support for the MDIO core - actually all I think that I need is for the ST bits to be 01 instead of 00 then I can use the core - shame its encrypted otherwise I am sure its a simple update. Looks like I am up for some bit bashing or write my own core unless anyone has some suggestions of a free working core (Octera seem to have one but I am assuming its costly)...