MIPS processor

Altera_Forum · ‎05-23-2011

HI. I am trying to write a vhdl code for execution of a single clock cycle MIPS processor. But the .scf file is showing me unexpected results. Maybe I am missing something.

The ALU_result is not showing the write result fron the read register data, and PC is not branching. Someone please check it it below and see where I'm wrong.

I am using bit 7 and 6 of the instruction to control the ALU. It needs to do only branch and add, and, + subtract.

Thx

R

>>

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY Execute IS

PORT( Read_data_1 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );

Read_data_2 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );

Sign_extend : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );

--ALUop : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 );

Zero : OUT STD_LOGIC;

Instruction : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

ALU_Result : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );

Add_Result : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );

PC_plus_4 : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );

clock, reset : IN STD_LOGIC );

END Execute;

ARCHITECTURE behavior OF Execute IS

SIGNAL Ainput, Binput : STD_LOGIC_VECTOR( 7 DOWNTO 0 );

SIGNAL OP : STD_LOGIC_VECTOR( 1 DOWNTO 0 );

SIGNAL ALU_output_mux : STD_LOGIC_VECTOR( 7 DOWNTO 0 );

SIGNAL Branch_Add : STD_LOGIC_VECTOR( 7 DOWNTO 0 );

BEGIN

Ainput <= Read_data_1;

-- ALU input mux

Binput <= Read_data_2;

OP < = Instruction(7 downto 6);

-- Generate Zero Flag

Zero <= '1'

WHEN ( ALU_output_mux( 7 DOWNTO 0 ) = "00000000" )

ELSE '0';

-- Select ALU output

ALU_result <= "000000" and ALU_output_mux( 7 DOWNTO 0 ) -- FLUSH

WHEN OP = "11"

ELSE ALU_output_mux( 7 DOWNTO 0 );

-- Adder to compute Branch Address

Branch_Add <= PC_plus_4( 7 DOWNTO 0 ) + Sign_extend( 7 DOWNTO 0 ) ;

Add_result <= Branch_Add( 7 DOWNTO 0);

--*************************************************************************************

PROCESS ( OP, Ainput, Binput )

BEGIN

-- Select ALU operation

CASE OP IS

WHEN "00" => ALU_output_mux <= Ainput + Binput;

WHEN "01" => ALU_output_mux <= Ainput and Binput;

WHEN "10" => ALU_output_mux <= Ainput - Binput;

WHEN "11" => ALU_output_mux <= Branch_Add;--branch;

WHEN OTHERS => ALU_output_mux <= "00000000" ;

END CASE;

END PROCESS;

END behavior;

Altera_Forum · ‎05-25-2011

i fear this is the wrong forum part for this topic.

Altera_Forum · ‎05-26-2011

Hi Karsten.

Thx 4ur concern. Like I said the simulation was showing unexpected results, the was something wrong with my control signals for the ALU. But I managed to get it right now.

Will post to the proper forum (of which I can't figure out another since this is software) in future.

Sharp sharp...:cool: