Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

MOS transistors, tran, tri1 and pullup in Verilog

Honored Contributor II

Hi guys. 


I am a student and i currently started studying Switch Level Modeling in Verilog. And there are some things, that i don't undestand. 


1. MOS transistors are represented as unidirectional gates. Their models are almost similar to bufif elements, rather then to the electrical models of transistors. What are the reasons of using such a poor model? (there is no need of using more complex model, or more complex model can't be implemented in terms of event-driven modeling) 


2. What it is the difference between using tri1 net and connecting to the wire a pullup gate? When should i use first and second? 


3. What is the difference between wire and connection of 2 elements with tran element? 


0 Kudos
0 Replies