Hello every body;How can i use the "times" function to make delay in my Nios2 code, as I built a VHDLcode that have a latency of 46 clk cycle, and I want to read its output after this latency. The illustration will be better if there are an example. Thanks.
If you built the HDL code yourself, you can definitely add a 'ready' signal which is set after the exact 46-clock delay.You can then conveniently use this signal in a poll loop or as an irq. Software delays are not the best choice, since they strongly depend on compiler and the way the delay is implemented.
Thanks Cris72 for your attention;I cannot use the ready signal as my code is designed to be in a pipe lined structure i.e every clock cycle there is an output, I just need to make a time delay in my soft code, here how can I use the usleep() function as you say. Thanks.
I don't quite get it. The code has latency of 46 cycles. So, even if the system is pipelined, it will still be restricted by this module to 1 output every 46 clks. Am I right?Anyway, it is a short interval. Using software to poll or delay does not seem appropriate. The software loop will need to be highly optimized. Any interrupt or deferred bus access would easily cause data loss. My opinion, software timing can be used only if we don't need accurate clock count and the interval is at least thousands of cycles apart. In your case, if latency is not an issue, it can be fed to a FIFO and read out much later. Otherwise, feed it to output without software intervention.