Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12436 Discussions

Marvell PHY Address? Aria V GX starter kit

Altera_Forum
Honored Contributor II
793 Views

I have an Aria V GX starter kit board with the Marvell PHY chip on it. I've got the TSE core hooked up RGMII mode with MDIO connected to the Marvell chip.  

 

I can read and write to the Marvell PHY using PHY address 0 (broadcast address), but not with any other PHY address. The config pins are not all set to ground on the board. So I would expect a non 0 PHY address to be boot strapped in the Marvell chip.  

 

Why I sniff the MDC/MDIO lines and look at MDIO transactions on a scope on the board update portal design that is included with the board, it looks like the Altera project also talks to the PHY on address 0.  

 

Why is the Marvell chip not getting a non 0 PHY address when config 2 pin is set to 2.5V?  

 

What am I missing?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
90 Views

For anyone interested in the Answer, the lower 2 config strap bits on the phy are what set the PHY Address. The Marvell PHY has a pretty elaborate boot strap configuration. When it comes out of reset it takes 3 samples on each config pin. If the pin is tied to ground, all three samples are 0. If the config pin is tied to VDD, all three bits are 1. If the config pin is tied to several available LED output pins, the 3 bits will be dependent on which LED it is connected to. Each of the available LED pins (multi use) generate a different 3 bit pattern at boot up then move into their normal link LED \ status LED function.  

 

If you need more info on this you will need the Marvell PHY spec sheet. Its pretty confusing stuff but basically if your lower two config pins are grounded, you PHY ADDR is going to be 0.  

 

I think Altera should have used something other than the broadcast address. But since there is only 1 PHY device on the board its not really a problem.
Reply