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Honored Contributor I
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Memory Test Failed when testing SRAM implemented in QSYS

I am trying to implement an interface for an external SRAM in Qsys. I used a Generic Tri-State Controller connected to a Tri-State Conduit Bridge. I am quite new to FPGAs, so this may not be the correct way to implement the SRAM interface. When I try to test the SRAM using the memory test application on NIOS I receive the error "-Data bus test failed at bit 0x1". 

 

I added a couple of lines to debug and I can see that the Pattern "1" is written to the base address 0x00080000, but when the base address is read the value is "1010101". 

 

My Qsys design is here.http://www.alteraforum.com/forum/attachment.php?attachmentid=9682&stc=1  

 

I would appreciate any help available. Thanks in advance.
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