How long is the duration of metastability in a flipflop? If metastability occurs in one cycle i.e. data edge coincides with clock edge and in the next cycle data is stable at the clock edge, will the output of flipflop still remain metastable in the next clock cycle?
--- Quote Start --- No, it should go stable again. If there is a risk of meta stable values in your system (other than synchronisers) you have a problem with your design. --- Quote End --- The data signal is generated at 122.88 MHz and sampled at 153.76 MHz via two synchronizers. Is it required to pulse stretch the data signal? The sampling clock is faster than the data signal.
--- Quote Start --- The data signal is generated at 122.88 MHz and sampled at 153.76 MHz via two synchronizers. Is it required to pulse stretch the data signal? The sampling clock is faster than the data signal. --- Quote End --- I think your problem is not metastability per se but how to pass data fom one clock domain to other. If you want to keep sampling rate as 122.88 then use dc fifo if you want to upsample to new rate then use filter
Technically metastability can last forever, which is why it's generally reported as an MTBF, or Mean Time Between Failures. That being said, you can get that MTBF up to trillions of years or more, making it pretty much a guarantee it won't happen.https://newwww.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp-01082-quartus-ii... That being said, Quartus can analyze metastability, not only by synchronizer but for the whole design: https://newwww.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii51018.pd...