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Altera_Forum
Honored Contributor I
1,405 Views

Methods of Halting/Stalling Nios II/f CPU, WAITREQUEST Scope and Access

Other than stopping the clock, is there a guaranteed way of halting or stalling the Nios II/f CPU without it losing its place (i.e., maintain PC, pipelines, and register values)? 

 

 

I see the WAITREQUEST signals on both the instruction and data buses, but can those be asserted without the CPU actively accessing an associated Avalon MM interface? In other words, will the CPU stall if WAITREQUEST is asserted even if it is NOT actively accessing memory? 

 

 

Here's my dilemma. I have tightly-coupled memories for both address and data. Both meet the requirements of 0 write latency, 1 cycle read latency, and usually no wait states. In other words, if the CPU isn't otherwise stalled, it will have full access. 

 

 

However, I'd like to unconditionally stall or halt the CPU in its current location so that I can overlay memory updates. 

 

 

I'm open to other recommendations or methods if you have them.  

 

Also, do you know of a good, detailed description of the scope and timing of the WAITREQUEST signal Much of the Nios hardware reference seems to lack sufficient technical detail.
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4 Replies
Altera_Forum
Honored Contributor I
49 Views

[edit: nevermind! I didn't see the part about "tightly coupled memory" where waitrequest isn't available to you. i.e. I missed the whole point of your question lol]

Altera_Forum
Honored Contributor I
49 Views

The Nios II uses the Avalon bus. You should check the Avalon bus documentation for more info. The details on how the Avalon bus works aren't described in the Nios documentation, but in a separate manual.

Altera_Forum
Honored Contributor I
49 Views

Never used it, and there is almost zero information on it, but "debugreq" sounds promising: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/nios2/n2cpu_nii5v1.pdf 

 

--- Quote Start ---  

 

The "Include debugreq and debugack signals" debug signals setting provides the following functionality. When on, the Nios II processor includes debug request and acknowledge signals. These signals let another device temporarily suspend the Nios II processor for debug purposes.  

The signals are exported to the top level of your Qsys system. 

 

--- Quote End ---  

 

 

But the more I think about it, I'd probably go for momentarily disabling the clock to the NIOS.
Altera_Forum
Honored Contributor I
49 Views

debugreq will not work because you need to insert BRET instruction into CPU pipeline in order to recover from debug mode.  

 

Stopping the clock would be the best for now unless you are using normal instruction/data masters.
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