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Altera_Forum
Honored Contributor I
1,514 Views

Minimal Cyclone V SE Testsystem on DE0-NANO-SOC: Uboot dies right after FPGA config

Hi, 

 

I made a minimum System in Quartus 15.1. The Qsys Systems consist only of an AvalonMM UART and a 8 bit PIO for the LEDs. The only bridge used is the lightweight HPS4FPGA one (in32bit mode). I got rid of all the complex FPGA2SDRAM bridge, and all the bells and whistles from the GHRD, because I will not need it in my application and want to start from a clean simple design. I enable I2C1 and HPS UART1 on top because I will need a secondary I2C bus layed out on the LTC connector of the board. I tested the settings for these in the original GHRD refernence design and that worked ok there. 

 

I copied all the memory and Qsys settings using screenshots from the GHRD settings by hand to my "lightweight" design and built the system. I also created a preloader and Uboot for it. Preloader and U-Boot comes up fine, recognizes the 1GB DDR3, can read from SDCARD etc. 

 

If I load the .rbf file in U-Boot and configure the FPGA, it configures the FPGA fine (the config done LED lits up), but exactly in that moment the U-Boot crashes and just does not take any input any more via the console. 

I do not remap the HPS0 UART to a different location, I just enable the second HPS UART and the I2C1 in the QSYS (I think this remapping of the UARTs and I2Cs would have happened anyhow in the preloader already, so if there would be a setting wrong I shouldn't have ended up in Uboot right?) 

 

Anyone has an idea where to start looking? 

 

Markus
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8 Replies
Altera_Forum
Honored Contributor I
55 Views

Markus - 

 

I have no guesses off the top of my head. This may be one of those situations where you need to go back to your baseline of the GHRD, make sure the system comes up properly with that, then start stripping things out one at a time until it breaks (or doesn't). Or you could start with what you have and start stripping things out from that one at a time until the system comes up properly. If you get down to having an FPGA image that does not interact with the HPS at all and the U-Boot still crashes then there may be a board-level problem. 

 

Sorry, that's the best I can come up with. 

 

Bob
Altera_Forum
Honored Contributor I
55 Views

Turns out it's the export of the 

 

.hps_0_f2h_cold_reset_req_reset_n ( ~hps_cold_reset ), // In : 

.hps_0_f2h_debug_reset_req_reset_n ( ~hps_debug_reset ), // In : 

.hps_0_f2h_warm_reset_req_reset_n ( ~hps_warm_reset ), // In : 

 

lines in the HPS. If I unexport them, U-Boot stays alive. I'm now struggling getting a working devicetree for my 4.0 Kernel. Oh my the sopc2dts sucks for 4.xx Kernels. Any hints on a start? 

 

The GHRD tree crashes later in the boot process as there is only the lightweight bridge and not the other stuff. How would the handoff in uboot look like for only enabling this very bridge? 

 

Markus
Altera_Forum
Honored Contributor I
55 Views

I don't mess with the software so can't help you with those issues. Sounds like you're making good progress, though. You might try posting your questions to the RocketBoards Forum: 

 

https://forum.rocketboards.org/
Altera_Forum
Honored Contributor I
55 Views

Unfortunately there is little feedback in the rocketboards forum. I think this forum here is way more active. I followed this instruction from the mailing list, and have at least my two I2C busses and the UARTs up & running now (at least they get recognized during boot, even an I2C RTC get probed and read out correctly). Maybe it's of help for somebody else: https://www.mail-archive.com/rfi@lists.rocketboards.org/msg00040.html 

 

I have to figure out why the UART and the PIO behind the bridge are not detected (right now it seem the whole brigde is ignored).
Altera_Forum
Honored Contributor I
55 Views

Still no luck, now the bridges are there in LINUX, but as soon as I write to the mmapped LW HPS2FPGA bridge, the system freezes.  

 

I have this minimum HPS System: 

http://www.dbox2ide.de/html/Minimum_Sys.png  

 

my toplevel file look like this: 

 

https://pastebin.com/qsdcifux (https://pastebin.com/qsdcifux

 

Preloader and uboot are updated, my uboot environment looks as follows (stupid Forum is limited to 10000 chars *sigh*) 

 

https://pastebin.com/qe8meftt (https://pastebin.com/qe8meftt

 

From the Handoff values, especially the l3remap=ff800000 l3remap_handoff=0x00000011 

 

I would say that only the lightweight bridge is enabled which would be correct.
Altera_Forum
Honored Contributor I
55 Views

My QSys is as follows: 

 

 

HPS Settings: (I only use the LW Bridge in 32 bit mode) 

 

http://www.dbox2ide.de/html/Settings_Qsys.png  

 

 

 

Peripheral Tab 

 

http://www.dbox2ide.de/html/Settings_Qsys_peripherals.png  

 

 

Input Clock Tab 

http://www.dbox2ide.de/html/Settings_Qsys_clocks.png  

 

 

 

Output Clock Tab 

http://www.dbox2ide.de/html/Qsys_Clock_out.png  

 

 

 

I've omitted the DDR settings. I assume the DDR Settings are correct as the LINUX runs stable.
Altera_Forum
Honored Contributor I
55 Views

Is there anything I'm overlooking? Do I need to enable any additional clocks? (I wouldn't know why, but I'm thankful for any hints). 

Markus
Altera_Forum
Honored Contributor I
55 Views

Sorry the links to picpaste died. It's not possible to add decent sized pictures into the forum, it is highly annoying. Also the 10000 Chars limit for pasting code.... 

 

I uploaded them elsewhere now
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