I have abandoned the HLS component top module design in relation to the post I wrote below. Therefore, I decided to design top module with Verilog and manually instantiate the generated HLS IP. I created new empty project in Quartus Prime 17.1 standard software and added HLS IP. Synthesis was run without error. However, a syntax error occurs in the system Verilog sub module of HLS IP in Modelsim-Intel simulator. I know this simulator version doesn't support mixed language simulation. Until now, I added -ghdl option to build.bat and could just check with wlf. Is there any method to simulate in case of me?