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Modular SGDMA Intel 64-bit multiple buffers/pages & Dynamic Address Translation?

Altera_Forum
Honored Contributor II
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Howdy Fellows, 

 

I am trying to implement an Ethernet driver for 64-bit Linux (3.5 kernel). I have used Modular SGDMA and everything works fine in a simple case scenarios when it sends or receives a single DMA buffer. However, I am not certain as for how to go about sending and receiving multiple buffers that come from different pages. In the HAL example, I don't think it makes any difference because there is no MMU and no different virtual <-> physical address translation (or is there?). A Linux example (from here — https://github.com/mapleelpam/sgdma-pcie-driver-demo/blob/master/demo-v1/sgdma_gen1x4.c) is a little bit better as it works with translation registers (see a2p_mask), however... it transfers only one page at a time and only one way. 

 

So the question is, how should I go about handling address translation register(s) for multiple DMA requests in flight (queued into DMA controller core), both to and from the host? By default, PCIe Core has 2 pages for translation registers... but I am not sure how exactly should I use them or if that's enough or not. Any advice/example is highly appreciated. 

 

Thanks, 

Vlad
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