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Modular SGDMA ST to memory streaming: write problem

Altera_Forum
Honored Contributor II
1,074 Views

Hi, 

I am trying out the modular SGDMA from the alterawiki (sorry, it doesn't let me post the link). Ultimately, the goal is to stream values from an ADC. Right now for testing purposes I have implemented a counter, which is just supplying consecutive 32-bit numbers. The streaming to the memory seems to work fine for the most part. However, regardless of the amount of data streamed, always the last 2kB are incompletely written to the memory. In those last 2kB, there are some patches of correct values, and some patches where the original memory content persists (i.e. is not overwritten with correct values). Those values that are written are in the right place. To me this appears to indicate that the missing values are in fact captured by the SGDMA, just for some reason not written to the memory - but the memory pointer is advancing regardless. Writing from the Nios to the memory always works. 

 

I have tried to change settings of the individual components (FIFO sizes, etc.), but was unable to pinpoint the problem. I am new to FPGA development, so any help is greatly appreciated! 

 

Details on the setup (using DE0-nano development board): Data input is through a dual clock FIFO from a 1MHz source to the SGDMA write master clocked at 100MHz. The SGDMA write master is directly connected to the SDRAM. The NiosII processor is also connected to the same SDRAM, via bridges as in the above example. I am not using on-chip memory. All clock signals are generated from one ALTPLL instance.
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Altera_Forum
Honored Contributor II
87 Views

Found the answer myself. I wasn't flushing the cpu cache! Modular SGDMA works great now for streaming.

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