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Multi-processing w/ Nios(II)

Altera_Forum
Honored Contributor II
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Hello to all - 

For a while I have been trying to instantiate and run a multiple Nios processor implementation. I have tried several different methods, but the most I have reached is about 70% success rate.  

I have tried an (old) example that was sent out by one of the groups at Altera which used a Y-cable to talk to the 2 serial ports on the Nios board, but could never get more than one processor to fire up at a time. When the second processor fired up it seemed to be have jumped into the middle of the code which was resident for the first processor. 

I did see an example from a group at NJIT where they connected the serial port to the first processor, then had this processor control and download programs to (4) other processors. They really did not provide details for implementation. This implementation is a little different than the Altera-provided example, which had direct communication through 2 serial ports 

 

So, I have several questions: 

 

1 - Has anyone had success with this ? If so, please enlighten. 

 

2 - I have seen several files with the 'boot...' prefix, but most of them were not text-readable. If I need to modify the bootfile, which of these should I be looking at ? 

 

3 - Any other information of use ? 

 

Target is the Stratix S/80 DSP board. 

 

Thanks, 

 

Jim
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Altera_Forum
Honored Contributor II
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Have you tried this with a later version of Nios I? 

Like Nios 3.2? 

 

The debug solution changed drastically. 

 

Also, Nios II is a significant change. you can download a trial version for free (see other forum post).
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Altera_Forum
Honored Contributor II
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Kerri - 

 

Thanks for the reply. 

 

When I mentioned Nios I, I meant Series I as opposed to Nios 1.0. I think the latest version of the Nios processor I tried was the distribution from about 5-6 months ago. 

One of the problems is that on 'Generate' (or, could be 'Compile' back in Quartus - havn't tried it in a while), even though the components have two different names, in one of those operations (i.e., 'Generate' or 'Compile') the build thinks the two part types are the same (which, in actuality they are), and deletes the instance of one of them.  

Even in the two-processor, two-serial port example Altera distributes, you have to hand massage a lot of the memory locations. 

 

Having said all of that, I'll still try the latest distribution of Quartus and Nios. 

 

Thanks, 

 

Jim
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Altera_Forum
Honored Contributor II
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Please email me off line.  

The example design that we used to distribute with 2 uarts for debugging hasn't been active in a long time. That's why I asked. 

 

khallbec@altera.com
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Altera_Forum
Honored Contributor II
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Jim, 

 

Not sure if this will help, but I've got a dual NiosI/II project working. For NiosII I'm using legacy support for ease of porting and smaller code size. 

 

Basically my primary processor is more full featured and runs out of main sdram and the other processor runs out of a 12KB onchip ram. I communicate with the Primary through JTAG and the secondary over the serial port. 

 

The two trade commands and data from a very simple mailbox system. (in onchip ram) 

 

Now that the secondary processor is debugged and fully functional I can alternately store the code directly as the contents of onchip ram instead of germs. So basically he just comes up and runs waiting for commands from the primary. 

 

Altera has promised enhanced multi-cpu support in upcoming version of NiosII IDE, so I'm going to use the NiosI setup I have now until this improved support emerges. 

 

If you think I could help, ask away. 

 

Ken
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