Hello,Is there anybody that used/have experience with Qsys to fit five Nios II on a Cyclone IV EP4CE22 FPGA? I could only fit one. I need to use SDRAM controller. I'd like to know how many Nios II have ever fit on 22,300 Logic Elements. Thanks, Alan
It will depend on the cpu type and options, IIRC you can get a cpu below 3000 LE.Remove everything you don't actually need - including most of (or all) the JTAG debug module. However, if you are trying to run 5 cpu reading code/data from SDRAM the working set better be small and fit in the (small) caches - otherwise all the cpu will always be waiting for memory.
--- Quote Start --- Which version of Nios? It should be easy to fit Nios II/e. On the other hand, why do You need so much softcores? --- Quote End --- I need to fit one Nios II/f plus four Nios II/e. The first Nios is a supervisor while the other four are slaves and required to manage real-time high-speed task execution.
The 'e' processors will be very slow indeed. Especially if executing code from SDRAM. You'd do better with a single 'f' processor executing an action for each slave in turn.For 'slave' cpu expose the soft reset lines to that the supervisor can take them out of reset once everything is initialised - so remove the JTAG debug module. If the code and 'normal' data for the slaves is small put both in 'tightly coupled' memory dual ported to the Avalon bus (so the supervisor can initialise it), remove their i-cache, probably remove their d-cache (depending on the access patterns to external memory). Altera don't give any examples of running very small code/data, nor anything with hard separation between code and data. You'll need to link readonly data with the read-write data, not with the code. Read the wiki pages about gcc, be prepared to build it yourself. There is also a 'hidden' config menu for the nios (which I'm willing to tell you about, but not how to get to!) which will let you further customise the cpu. In particular it lets you remove the dynamic branch predictor from the 'f'. For 'real time' work you probably don't want it.
Hey,I did not exactly get the meaning of above explanation. I have 4 cores, all Nios-e. One common JTAG port for all 4 cores. What I am doing till now: Reset vectors for all 4 cores are set to SDRAM. When I need to run the application dedicated for a particular core, I do right click -> run as-> Nios II Hardware. This way I have to run all 4 apps individually and therefore they start at different times. Is their any way to start them all together ??? Also I am not able to run all cores simultaneously. The newest core being programmed freezes the already running core. Please suggest.
Dunno. I don't use JTAG.At a guess either the JTAG download is resetting all of the cpus, or they are being starved of some Avalon resource. You can expose the soft reset lines of the nios cpu and connect them to an avalon slave. Then arrange that system reset (and JTAG reset) leaves all but one in reset. Use the jtag to load a single image that contains the code/data that all the separate cpus will run. When the first cpu runs get it to take the other ones out of reset.
Hi dsl,Thanks for those guidelines. But sorry, I don't know how to create a single image of four different applications that needs to be run on four different cores. Please suggest. Thanks
You sure you use different sysid? And also are you sure, that you've set the reset vectors to different places, so no other core write to each other core reserved space?
Hi Socrates,Thanks for guidance. I did not use separate SYSID qsys components for each core, but i assigned different "NIOSII -> Advanced Feature -> cpuid control register value" to each NIOS core. Is SYSID component necessary ? And yes I did set the reset vectors to different address. I gave 64KB SDRAM memory to each core. Also I have a question, how to figure out whether the stack, heap and other memory parts of different cores are not coinciding. As far I know, NIOS II EDS for Eclipse throws an error if it is so.
Hi,I have my SDRAM at 0x80_0000. 1st Core: Reset Vector: 0x80_0000 Exception Vector: 0x80_0020 2nd Core: Reset Vector: 0x81_0000 Exception Vector: 0x81_0020 3rd Core: Reset Vector: 0x82_0000 Exception Vector: 0x82_0020 4th Core: Reset Vector: 0x83_0000 Exception Vector: 0x83_0020. Though when I run my 1st core, it runs & says "starting at address 0x80_0020". But when I run my 2nd core, it freezes the 1st core and itself runs in a weird way and says "starting at address 0x80_0000". Can anyone please suggest why 2nd core is starting to run at 0x80_0020. It should start at 0x81_0020.
It could be a problem in your link script. Check that the application for the second core is indeed mapped in the 0x81xxxx range in the link script. Did you create separate link sections for all 4 cores?
It looks okay to me. You can always try and run the nm command on the generated elf files to check that everything is put in the correct memory area, but I don't see any problem in your linker script settings.My next suggestion would be to put some signaltap probes around the two CPU's Avalon masters to try and figure out what they are doing and why your first CPU is freezing.