Multiple interrupts on single PIO input event

Altera_Forum · ‎05-26-2014

Hi,

I've been trying to use User push buttons in an applications. I've modified the Standard Ethernet Example from Altera to include VIC and shadow registers.

The design example configures the push buttons to generate an interrupt when pushed. The problem is that every push generates more than one interrupts even after I've cleared the interrupt in my ISR. Is there any documented way/Example of doing this? I've pasted my code below for reference.

Thanks!

Environment

------------

13.1 Quartus tools.

Standard Ethernet Example from Altera modified to add VIC and shadow registers.

Hello World Nios II application example.

Cyclone III (EP3C120F780C7) device.

Test Code

---------

volatile int count = 0;
static void handle_interrupt()
{
        // Clear all interrupts.
	IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PERIPHERAL_SUBSYSTEM_BUTTON_PIO_BASE, 0xF);
	count++;
}
static void register_interrupt()
{
	// Enable all 4 button interrupts.
	IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PERIPHERAL_SUBSYSTEM_BUTTON_PIO_BASE, 0xF);
	// Register handler.
	alt_ic_isr_register(PERIPHERAL_SUBSYSTEM_BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID,
						PERIPHERAL_SUBSYSTEM_BUTTON_PIO_IRQ,
						handle_interrupt, NULL, 0x0);
	alt_ic_irq_enable(PERIPHERAL_SUBSYSTEM_BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID,
					  PERIPHERAL_SUBSYSTEM_BUTTON_PIO_IRQ);
  }
int main()
{
	// Register PIO Interrupts.
	register_interrupt();
	printf("Hello from Nios II!\n");
	// Loop forever.
	while (1);
  return 0;
}

Altera_Forum · ‎05-26-2014

Is the edge capture feature enabled in your PIO configuration? Otherwise the edge cap register is not implemented and irq is level sensitive, namely it continuously triggers as long as the input is active.

Altera_Forum · ‎05-26-2014

Yes, Edge Capture is enabled and the interrupts are edge triggered. I've tried both Rising and Falling edges to no effect

Altera_Forum · ‎08-14-2014

Try resetting the interrupts on the PIO. To do that, write any value to the IRQ reset register located on PIO register offset 0xc

Altera_Forum · ‎07-19-2015

Try de-bouncing the switches, your processor is most likely responding so fast that it is capturing multiple events as they are cleared very quickly by the processor. Switches can generate multiple events separated by milliseconds. Since your processor responds in microseconds it can capture multiple events.