Re: *NEWBIE* User Logic

Altera_Forum · ‎12-14-2004

Hello,

I created a very simple user logic. I takes the input, adds 1 to it and write it to the output.

timescale 1ns / 100ps
module mytestmodule (
               // inputs:
    address,
                write_data,
               // outputs:
                read_data
             );
  output   read_data;
  input    write_data;
  input    address;
  wire     read_data;
  assign read_data = write_data + 1;
endmodule

Now I want to test it

#include <stdio.h># include <C:\altera\kits\nios2\bin\eclipse\workspace\uCLinux_Kernel\build\include\nios2_system.h>
# define ul_base 0x009208E0
typedef volatile struct
 {
  unsigned char adress; // 2 bit address
  unsigned long int write_data; // 32 bit writeable data
  unsigned long int read_data; // 32 bit readable data
 } userlogic;
 
int main (void) {
 userlogic *ul = ul_base;
 
 
 unsigned long int i;
 for (i = 0; i <= 4; i++) {
   ul->write_data = i;
   printf("write_data=%ld --> read_data=%ld\n", i, ul->read_data);
 }
 return 0;
 
}

I doesn't work and I don't know, where I have to begin to find the error. Can anyone help me?

Altera_Forum · ‎12-14-2004

I'll assume the hardware works (I'm one of the few North Americans that use VHDL lol).

But looking at your software, if you are using data cache, then you are not bypassing it. For register access declare your pointers volatile (so they don't get synthesized away), and use the IORD and IOWR commands to bypass the data cache. Here is the syntax:

IORD(base, offset);

IOWR(base,offset,data);

Base is the base address of your hardware, offset is the address within the address space of your hardware (offset from the base), and data is the data you will be writing. These are the 32 bit calls, they have others for 8 and 16 bit operations as well.

Cheers.

Altera_Forum · ‎12-14-2004

Try latching your write data.

--Scott

Altera_Forum · ‎12-16-2004

OK, I've included io.h to use IORD and IOWR. But now I need SYSTEM_BUS_WIDTH. Where can I find this?

Altera_Forum · ‎12-16-2004

BadOmen's suggestion requires that you try building a basic Nios II standalone application using Altera's HAL.

In fact, I think that might be a better way to go to test out your hardware first before jumping into Linux.

Try taking a look at some of their hello world examples to start off with... I think they also have some PIO examples which should give you a good starting point as well...

Altera_Forum · ‎12-17-2004

Write data isn't guaranteed to be stable when write is negated.

So you need to latch ... Try this:

module mytestmodule (clk, address, write, writedata, readdata);
input clk;
input  address;
input write;
input    writedata;
output   readdata;
wire clk;
wire  address;
wire write;
wire  writedata;
wire  readdata;
reg  dreg;
always @(posedge clk)
    if (write) dreg <= writedata;
assign readdata = dreg + 1;
endmodule

--Scott

Altera_Forum · ‎12-22-2004

Now it works! Thank you!!

Because Linux don't have IORD nor IOWR I used Bit-31 Cache Bypass.

Altera_Forum · ‎12-23-2004

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

Because Linux don't have IORD nor IOWR ...[/b]

--- Quote End ---

Actually Linux does have such facility, but with different names.

to read and write from device memory: readx can be b, w, or l. Please check linux header file io.h.

Altera_Forum · ‎01-18-2005

hello BadOmen

can you tell me the exact mean of the "volatile"?

Thank you!