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Altera_Forum
Honored Contributor I
878 Views

NIOS 2 EPCQ and SDRAM for program code

For this application note 

https://www.altera.com/en_us/pdfs/literature/an/an736.pdf 

It describes how to boot NIOS from EPCQ flash. Program is in the EPCQ flash. In one of the examples in the app note, they show how the program is loaded from the EPCQ to the on chip memory. The clock for the EPCQ flash controller is 25mhz

I have a DE1-SOC board which has SDRAM with the FPGA. I could run NIOS and run programs from the ON chip memory. I could access the SDRAM for data writing and reading. NIOS system runs with the 143mhz because of the SDRAM. 

 

I need to add the EPCQ flash controller with the system while working with its max freq 25MHz. 

I don't know how to load the program from the EPCQ to the SDRAM and then run the program from the SDRAM. I want help in understanding this. 

 

Thanks
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5 Replies
Altera_Forum
Honored Contributor I
47 Views

Use a Clock Bridge and set the 'Explicit clock rate' to 25MHz. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
47 Views

Do you mean like the following pic?http://www.alteraforum.com/forum/attachment.php?attachmentid=12361&stc=1  

I connected the input clock of the clock bridge to the NIOS clock
Altera_Forum
Honored Contributor I
47 Views

That should do it. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
47 Views

Dear Sherif123, 

Does this method work?
Altera_Forum
Honored Contributor I
47 Views

 

--- Quote Start ---  

Dear Sherif123, 

Does this method work? 

--- Quote End ---  

 

 

I did not try it yet. But I think it may not work. 

I think I just need to connect the EPCS controller to its clk and the QSYS interconnect will automatically add fifos for clk domain crossing.
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