NIOS EDS doesn't find cpu on a system with DDR3 controller

[Altera_Forum]

Hello everyone. 

 I'm trying to migrate a system made on a Cyclone II fpga for a Stratix IV GX. The system includes two DDR controllers, that i have exchanged for two DDR UniPHY controllers, one for top port, and another for bottom port.  After a lot of suffering, i could compile the project, but i had no luck when running the project.  I've been stuck on this problem for almost 20 hours and no progress:  When I try to connect onto the JTAG UART interface, the NIOS EDS says that he cannot find the cpuid, neither the timestamp on the defined base addresses. If i try to ignore them and then run, it's says that the processor does not respond, and shout "leaving target processor paused".  If someone could help me it would be very appreciated. I already tried to start one project from stratch, only with a nios and one controller, happened the same thing.  I'm attaching the project.  Sorry if i didn't give enough information, i'm a newcomer on this part of FPGAs system.  Thank you!

[Altera_Forum]

finally I had some success on running only with NIOS, by using the "External Memory Interface Handbook Volume 5 - Section II. UniPHY Design Tutorials" guide! Let's see if i can add the custom module...

[Altera_Forum]

It's working! Problem: wrong assignment of pins! Used golden_top script that is on the CD, and everything worked *almost* flawlessly, except for some pins that were assigned wrong on this script too ¬¬ then I've used a script dedicated for bottom port of DDR-3 that exists on a project on altera's website, and everything worked fine.