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Altera_Forum
Honored Contributor I
755 Views

NIOS + Eth minimum resources utilization

Hi to all, 

I just registerd to the forum! :) 

I'm familiar with FPGAs but I'm starting to use NIOS in these days. 

The system that I would like to realize uses the Ethernet to receive data from a PC and NIOS should pass this data to custom logic inside the FPGA. 

My first constraint is to use less resources as possible for the NIOS+ETH system, to do so my first question is: 

is it possible for NIOS to use the external DDR3 (my stratix IV based board has an external DIM module) as data and instruction memory(to reduce the on_chip memory) ? To be more clear it is possible on boot to load the efi on the DDR and use "only" the external memory? 

 

I'm trying to adapt some tutorials\examples with uniphy DDR3 controller and triple speed ethernet with an architecture like: 

1) onchip_memory + nios + tse + other peripherals running at 125MHz (for the tse) 

2) uniphy DDR3 controller running at 333MHz 

3) a clock crossing bridge with m0 connected to uniphy avl port and s0 to both instruction master and data master. 

 

If I don't connect clock crossing bridge to s0 the system seems to run properly ( system id and timestamp match) but when all is connected system id and timestamp are no longer found :( 

There is some example quite similar to my architecture that I can use as reference design? 

 

Thanks!
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2 Replies
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

Hi to all, 

I just registerd to the forum! :) 

 

--- Quote End ---  

 

Welcome! 

 

--- Quote Start ---  

 

is it possible for NIOS to use the external DDR3 (my stratix IV based board has an external DIM module) as data and instruction memory(to reduce the on_chip memory) ? To be more clear it is possible on boot to load the efi on the DDR and use "only" the external memory? 

 

--- Quote End ---  

 

Yes there is no problem with doing that, but the NIOS program needs to get copied into DDR one way or another. If the NIOS can't boot from a small (parallel) flash, then you will likely need an onchip memory (ROM) with a bootloader program in it. This is the approach used by the EPCS NIOS boot method, where the small bootloader has the NIOS copy the executable from EPCS flash to your external memory. 

 

http://www.altera.com/support/examples/nios2/exm-alt-boot-methods.html 

 

Something else to consider is that minimizing resources including trimming the NIOS cache is going to result in very low performance when executing from DDR. 

 

 

--- Quote Start ---  

 

If I don't connect clock crossing bridge to s0 the system seems to run properly ( system id and timestamp match) but when all is connected system id and timestamp are no longer found :( 

 

--- Quote End ---  

 

Did you regenerate the BSP after changing the FPGA? It sounds like the base address of those peripherals changed. 

 

 

--- Quote Start ---  

 

There is some example quite similar to my architecture that I can use as reference design? 

 

--- Quote End ---  

 

There is a couple good examples: 

http://www.altera.com/support/examples/nios2/exm-net-std-de.html 

http://www.alterawiki.com/wiki/nios_ii_udp_offload_example
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

 

 

Yes there is no problem with doing that, but the NIOS program needs to get copied into DDR one way or another. If the NIOS can't boot from a small (parallel) flash, then you will likely need an onchip memory (ROM) with a bootloader program in it. This is the approach used by the EPCS NIOS boot method, where the small bootloader has the NIOS copy the executable from EPCS flash to your external memory. 

 

http://www.altera.com/support/examples/nios2/exm-alt-boot-methods.html 

 

--- Quote End ---  

 

 

reading the documentation about boot loaders I understood that the standard boot loader should be able to load the program from the flash to the DDR RAM, but it is required a small amount of onchip memory to run the bootloader, it is right?  

 

--- Quote Start ---  

 

Something else to consider is that minimizing resources including trimming the NIOS cache is going to result in very low performance when executing from DDR. 

 

--- Quote End ---  

 

 

how much cache it is "advisable" to use? In my system Nios will only receive packets from UDP and make data available to FPGA custom logic and vice versa.  

 

--- Quote Start ---  

 

Did you regenerate the BSP after changing the FPGA? It sounds like the base address of those peripherals changed. 

 

--- Quote End ---  

 

 

of course yes! 

 

 

--- Quote Start ---  

 

There is a couple good examples: 

http://www.altera.com/support/examples/nios2/exm-net-std-de.html 

http://www.alterawiki.com/wiki/nios_ii_udp_offload_example 

 

--- Quote End ---  

 

 

thanks! the alterawiki example seems very interesting
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