NIOS + FPGA logic co-simulations

[amildm]

Hi All,

 Is it possible to simulate NIOS SW along with FPGA logic (HDL code)? How? Is there such Design Example? Where could it be downloaded from?

Thank you!

[EBERLAZARE_I_Intel · Accepted solution]

Hi,

You can check the document below , and see if this is what you are looking for:

https://www.intel.com/content/www/us/en/docs/programmable/683689/current/simulating-embedded-processor-designs.html

[EBERLAZARE_I_Intel]

Hi,

May I know if you require further help?