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NIOS GPIO and metastability: doubt...

Altera_Forum
Honored Contributor II
833 Views

Hi everyone! 

 

Just a simple confirmation. 

We had implemented an NIOS project with some GPIOs (the ones provided in QSYS) 

The interfaces are asynchronous respect to the internal clock domain. 

 

I assume initially that the input IPs for the NIOS had a double flipflop but looking at the RTL netlist I notice that there is combinatorial logic already at the input or after the first flip flop. :-/ 

 

So the NIOS GPIO is done basically for syncronous interfaces ​with the NIOS Clock and i case of asyncronous it is expect that the desinger manage the resampling for metastability outside? 

 

Is my assumption correct? 

 

thanks in advance 

Ale
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1 Reply
Altera_Forum
Honored Contributor II
107 Views

No - you don't necessarily need to manage this 'outside' the Nios core. You could chose to manage any 'metastability' in software in a similar way to how you might manage button bounce. 

 

In practice, when your software request the port value it will be given a value, '0' or '1'. If this is at a point when the port level is changing you will still be given a '0' or '1'. Whether either is right is debatable since the logic level is changing. However, the point is that the software will report a genuine value - '0' or '1'. Should you request the port value again immediately, the level will have settled and the new value may or may not have changed. 

 

Managing this outside the Nios core is perfectly fine too. It's down to the designer to design any interface on or off the device appropriately to the requirements of that interface. 

 

Cheers, 

Alex
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