I have the Cyclone V E Development Kit, and am trying to implement a NIOS II processor that starts in the CFI flash, gets copied to the DDR3 then runs off the external DDR3. I am pretty sure I have the QSYS setup correct seen there in the first picture. The reset vector is set to the and exception vectors are set in the second picture. The BSP linker sections are shown in the next picture. Everything is unchecked in the BSP Hal Linker section (the allow_code_at_reset and enable_alt_load) which is what the NIOS alternate boot method document from Altera says to do found here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pd...
My question is how am I supposed to run the debugger from the Nios II EDS, since the boot method document only seems to specify how to place the project on the board permanently? When I try to debug it, I first flash my FPGA using the Quartus Programmer which succeeds. Then I go into Eclipse for NIOS and try to debug the project, which is just the HelloWorld example using my sopcinfo file, and I always get this error shown in the photo. Obviously I'm missing something basic, and I'd appreciate any insight, Thanks!
- You may face such issues when our board is in reset state and we are trying to program the .elf, Check the dip switch to which the rest pin is connected, Should be disable.
- Check the clock pin connection.
- Re-check if we importing correct .sopcinfo file?
- Try to recreate the eclipse project.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
Can you please check the following:
1- The target connections and solve the names is required.
2- The USB cable (it should be OK since you managed to program the FPGA).
3- The JTAG-UART availability, it might be busy.
Can you please share a screen shoot of the targeted connections list? This error is very generic error.