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Altera_Forum
Honored Contributor I
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NIOS II Multi-Processor System's On-chip Memory

Hi, 

 

I was just wondering if anyone can help me in finding the answer of the following given question; 

 

Q. Suppose we have a NIOS II Multi-Processor System and all the processors are executing a same set of instructions simultaneously, let's take an example of 5 cores in which one is master core and other four are slave cores. There is only ONE shared On-Chip memory for all the cores. If a master core declares an array of 1024 elements in its own code, how could the master core share the 'ADDRESS' of this array with other cores?? 

 

I want to split the declared array length among four cores equally so that each core can operate on the given subset of data, like in this case, 256 elements for each core.  

 

So, simply I wanna know how can a NIOS II core share its variable or array location (address) with other cores so that they can make use of it?? 

 

Looking forward to hear from you soon. Thank you in advance..
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10 Replies
Altera_Forum
Honored Contributor I
72 Views

It's all set up in the hardware through multi-mastering. In Qsys, connect all the cores to the on-chip memory. The base address for the memory for each core can be the same or unique for each one. It doesn't matter because each master has its own memory map. Then, in the BSP editor for each core, make sure the linker script is set up for the correct offset to the appropriate location in the memory.

Altera_Forum
Honored Contributor I
72 Views

You can have a fixed location in memory that you share between all your processors for message passing. You will also need a hardware mutex to ensure that two processors won't try to access it simultaneously. I think that Altera has a hardware mutex core designed for multiprocessor communication.

Altera_Forum
Honored Contributor I
72 Views

 

--- Quote Start ---  

You can have a fixed location in memory that you share between all your processors for message passing. You will also need a hardware mutex to ensure that two processors won't try to access it simultaneously. I think that Altera has a hardware mutex core designed for multiprocessor communication. 

--- Quote End ---  

 

 

You mean we can assign 'shared memory region' within the given On-chip memory?? If this is the case, then who will assign this region and how would other cores know about it? 

 

And if we manage to do that, even then how master core inform other cores about the memory location of the declared array?  

Simply, if there is an array of 1024 elements in the on-chip memory (shared), how each core will get to know about the starting and ending addresses of its part from those 1024 elements? hopefully you got the idea what I'm trying to say :-) Each core will process 256 elements in parallel with other cores so they should know where to find those 256 elements within the 1024 elements..
Altera_Forum
Honored Contributor I
72 Views

 

--- Quote Start ---  

It's all set up in the hardware through multi-mastering. In Qsys, connect all the cores to the on-chip memory. The base address for the memory for each core can be the same or unique for each one. It doesn't matter because each master has its own memory map. Then, in the BSP editor for each core, make sure the linker script is set up for the correct offset to the appropriate location in the memory. 

--- Quote End ---  

 

 

I guess you didn't get my point, I know what you are saying but the problem is 'To Access a Shared RAM' containing data like an array of 1024 elements which will be processed by four individual cores simultaneously. This 1024 elements array will be divided into four equal parts resulting in 256 elements for each core. This array is defined by the fifth core which is the master core and my question is 'How this master core inform the other four cores the address of this array, so that they can process their assigned 256 elements only and stop afterwards..
Altera_Forum
Honored Contributor I
72 Views

What I meant is that you must define your own message protocol for all the CPUs to communicate. This message protocol can use a small block of shared memory, and the address to that block would have to be fixed in hardware and hard coded in the software on all CPUs. Each time a CPU has a message to send to the others, it would signal it through a specific byte, or you could also create a custom HDL block that would send an interrupt to the other CPUs. The other CPUs read that byte, and then the message. 

Once you have defined a communication protocol between the CPUs, you just have to send messages saying when some data is available, at what address and what needs to be done to it.
Altera_Forum
Honored Contributor I
72 Views

You wrote "all the processors are executing a same set of instructions simultaneously", by it I assume you mean the program, therefore all cores run the same program. 

That also implies the same variables. 

This is called Symmetrical Multi-processing (SMP) vs. each core running its own program (AMP: Asymmetrical Multi-Processing). 

As they run the same program and share the same data, the program itself must have provision to use the core ID (or number) to select core-specific operations / memory accesses. 

In your specific requirement about splitting the array, use the core ID# as an offset: 

1 - Declare your array as a 1024 one, e.g. int Array[1024]; 

2 - The slave cores (#1->#4) access their area using this point: 

MyPtr = &Array[(CoreID-1)*256]; 

Same program, same array, but different accesses by the individual cores 

 

If your application needs synchronization, messages, queues, parallel processing, shared resources access, etc. you should seriously look at using a SMP RTOS. 

Regards
Altera_Forum
Honored Contributor I
72 Views

Dear ericv, there is one master core and four slave cores. Master core declares this array in its own code which slave cores have no information about, But this array needs to be accessed by all the slave cores.. Yes you are right that we can calculate the offset on the basis of core ID but for that,the base address must be known to slave cores. so, how the base address of this array will be shared with the slave cores if there is a shared memory in the system??

Altera_Forum
Honored Contributor I
72 Views

rizwanfazal, 

 

Back to you initial posting: 

"There is only ONE shared On-Chip memory for all the cores" 

 

As it is shared, it can be viewed/written/accessible by all cores. 

In S/W, memory region/mapping/section are resolved during the build process with a file supplied to the linker. 

That file is called a linker script, or command, or scatter file, or ... 

That file supply to the "code" the address of the shared memory. 

 

If the cores don't have the shared memory mapped at the same base address, then you'll have to use unique linker files for each cores. 

This also means you cannot use the same program on all cores (original post: all the processors are executing a same set of instructions simultaneously). 

That is unless the code accesses at run time the shared memory through a hard-coded addresses according to the core# . 

 

Regards
Altera_Forum
Honored Contributor I
72 Views

Can you please share with me any simple sample code written in C in which I can see that all happening??

Altera_Forum
Honored Contributor I
72 Views

rizwanfazal 

 

Here's the basic info. 

Look in the the GCC compiler & GNU linker documentation for the proper syntax & usage. 

 

1 - Declare the shared array in your "C" code with something alike: 

char Array[???] __attribute__ ((section ("MySharedBuffer"))); 

 

2 - In the linker script file, define the memory address & range occupied by the shared memory and assign the section: 

MEMORY 

SH_MEM (rwx) : ORIGIN = 0x????? , LENGTH= ??K; 

.... 

SECTIONS 

MySharedBuffer : 

*(MySharedBuffer) 

} > SH_MEM; 

... 

 

Regards
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