Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

NIOS II Processing Getting Reset with SDRAM

Honored Contributor II

I have developed a hardware design with Nios II processor using the DE0 board with Quartus v12. I am using a cpu, a sys clk timer, an interval timer, jtag uart, system id, sdram and pios. . When I run the nios program in C with SDRAM, it gets reset periodically after every 3.64 s (approx). I do not encounter this problem without SDRAM. Is there any setting that I need to change in order to prevent this?

0 Kudos
1 Reply
Honored Contributor II

Either your software has a bug, or your hardware has a bug. Assuming you didn't add a watchdog, theres no "feature" anywhere that is going to reset your system periodically.  


The hardware bug would be in the area of the SDRAM and is easiest to test, simply by adding the Avalon-MM Traffic Generator and BIST Engine and let it run for a bit.