Hello Frined's,My Nios-ii System taking continuous interrupt at 1 mhz from external FPGA module with in same FPGA (Altera DE2_115 board), but when i forwarding this interrupt signal on another external pins, most of the interrupt signal's are lost or missing. Suggest me what went wrong or what precaution i should take to cater this problem. Regards Kaushal
Use a lower interrupt frequency? If the CPU is running at 100MHz it would mean it would have only 100 cycles to process the interrupt, and I really don't think that's enough.Why do you need such a high interrupt frequency?
I am getting Bunch of data around 2mb from other board along with clock i want to collect this data and convert in to TCP packets.so first i collect this data which comes at 1mhz and store it in local 2D-Array.I am facing problem in data collection or is there other way to collect it...?
DMA - or at least a fifo that only requests an interrupt when it cintains a moderate amount of data.You might manage that interrupt rate if it is your only interrupt source, and you handle it in assembler directly at the 'trap' address and using registers that don't have to be saved. Anything like the jtag uart interrupt probably disables interrupts for longer than 100 clocks.